Huawei Technologies Co., Limited

Nokia Corporation

Kimmo Koli

Juha Rakkola

Jukka Salminen

Pertti Tolonen

Teemu Salo

Mikko John Englund

A Radio Frequency (RF) receiver is provided. The RF receiver is configured to simultaneously receive at least two radio frequency bands with a single receiver path. The RF receiver comprises a single local oscillator (LO), and the RF receiver is configured to filter a received signal using a complex filter having a variable center frequency. In accordance with another aspect, many RF receivers are combined to form an aggregate carrier receiver.

Radio frequency receiver for carrier aggregation

A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

Receiver for a telecommunication system

A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core, and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle.

Double data rate interpolating analog to digital converter

A flash analog to digital converter (ADC) includes a first, second, and third double data rate comparator core configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the comparator core. An inverted comparator clock coupled to the third comparator core reduces kickback noise. The ADC includes a first and a second floating voltage reference configured to shift a voltage of a differential comparator input by a fixed amount, and produce the first and second differential input signal. The third comparator core is cross coupled between the first and second comparator core.

Double data rate time interpolating quantizer with reduced kickback noise

An analogue to digital converter uses charge sampling in combination with a successive approximation conversion technique in order to combine anti-alias filtering and quadrature downconversion functions into the data converter. The conversion method is an energy-efficient realization for wide-band radio systems with moderate resolution specifications such as 4G or ultra-wideband radio (UWB). The converter uses two capacitor matrices, one to perform charge sampling, and one to be used simultaneously in the successive approximation technique, so that full use of an input signal is made and efficiency is maximized.

Analogue-to-digital converter

Various embodiments are disclosed relating to techniques of filtering and down-converting a received signal. In accordance with an example embodiment of the present invention, an analog signal may be received and amplified in a transconductance amplifier. The amplified signal may be connected to a switching arrangement and an impedance circuit connected in series, and frequency down-converted in a second circuit. The resulting analog base band signal may be fed back to a base band input between the switching arrangement and the impedance circuit.

Apparatus comprising frequency selective circuit and method

A delta-sigma A/D converter includes a D/A converter realized with a mixed-mode comb filter connected in a feedback loop from the output of the A/D converter to the input of the A/D converter. The D/A converter is configured to predistort a feedback signal. The converter further includes an analogue filter at the input of the A/D converter. The analogue filter is configured to cancel the predistortion of the feedback signal.

Performance of A/D converter and receiver

The invention relates to an electronic device and a method of enhancing character input in an electronic device comprising a set of keys. The method comprises associating a group of characters with at least one key; detecting repeated presses of a key; detecting whether the key has been touched continuously during the repeated presses of the key; and interpreting the characters corresponding to the key presses in the group of characters associated with the key on the basis of the detections.

Enhancing character input in electronic device

An energy-efficient acceleration measurement system is presented. The system includes an accelerometer, responsive to acceleration of the system, for providing an accelerometer output signal having a magnitude indicative of at least one component of the acceleration. A motion detector is responsive to the accelerometer output signal, and provides a processor interrupt signal, but only if the magnitude of acceleration reaches a threshold. The processor, responsive to the processor interrupt signal, measures the acceleration with higher accuracy than the motion detector is capable of, but in a way that consumes more power than was needed by the motion detector.

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Helsinki, Finland

Kimmo Koli