Kabushiki Kaisha Toshiba

Sony Corporation

Shibaura Institute of Technology

Kimiyoshi Usami

Masahiro Kanazawa

Naoyuki Kawabe

Toshiyuki Furusawa

Masayuki Koizumi

Hidemasa Zama

Takashi Ishikawa

Takeshi Kitahara

Daisuke Sonoda

Fumihiro Minami

Hiroshi Tanaka

Mutsunori Igarashi

Seiichi Nishio

Chiharu Mizuno

Masaru Kudo

Yasuyuki Nozuyama

Nobu Matsumoto

Jun-ichi Tsujimoto

Atsushi Kageshima

Tohru Sasaki

Naohito Kojima

Yukinori Muroya

Yukio Sugeno

Atsushi Horie

Yukiko Ito

Aya Ishii

The present technique relates to a non-volatile memory circuit ensuring a small size and low power consumption while maintaining stable write. A slave latch is provided in an NVDFF, and magnetoresistive elements are connected to the slave latch. A store operation for writing information stored in the slave latch to the magnetoresistive elements is performed before power interruption, and a restore operation for reading out information stored in the magnetoresistive elements to the slave latch is performed at a time of return. The store operation and the restore operation use different paths between the slave latch and the magnetoresistive element. The present technique is applicable to a non-volatile memory circuit.

Non-volatile memory circuit

This invention relates to a semiconductor device that reduces energy consumed to write data to a nonvolatile storing section. A write control circuitstores the same data as that held in MTJ elements MTJand MTJ. In a store operation storing the data held in a slave latchinto the MTJ elements MTJand MTJ, the write control circuitcompares the data stored therein with the data held in the slave latchto control whether or not to write the data to the MTJ elements MTJand MTJ. If the internally stored data coincides with the data held in the slave latch, the write control circuitperforms control not to write the data to the MTJ elements MTJand MTJ

Semiconductor device to reduce energy consumed to write data

A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

Semiconductor integrated circuit having an oblique global signal wiring and semiconductor integrated circuit wiring method

A power-off controlling circuit and a power-off controlling method that control power-off of an integrated circuit based on the size of leakage currents. The power-off controlling circuit includes a model circuit section that includes a model circuit made by modeling a basic circuit of an integrated circuit, a voltage comparing circuit section that compares an output voltage charged by a leakage current occurred at the model circuit and a preset reference voltage, a decision circuit section that measures an arrival time until the output voltage reaches the reference voltage from the compared result and decides a size of the leakage current from the measured result, and a power-off controlling circuit section that controls power-off of the integrated circuit on the basis of the decided size of the leakage current.

Power off controlling circuit and power-off controlling method

A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Semiconductor integrated circuit with reduced leakage current

A computer aided design system and a method for clock gated logic circuits, a computer-readable medium for storing the same and a gated clock circuit are provided in which the clock skew is suppressed within a tolerable level without increasing the electric power consumption.

Computer aided design system and computer-readable medium storing a program for designing clock gated logic circuits and gated clock circuit

A logic circuit design equipment and a logic circuit design method include analyzing input states of all of first cells, respectively, analyzing leakage currents of all of first cells in a case where each first cell is high Vth cell showing a small leakage current at a low speed operation and low Vth cell showing a large leakage current at a high speed operation, respectively, and substituting the first cells for second cells within a range satisfying a timing restriction. Herein, a threshold of the second cell is different from a threshold of the first cell.

Logic circuit design equipment and method for designing logic circuit for reducing leakage current

Semiconductor integrated circuit, logic operation circuit, and flip flop

A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefor in which a first cell to which multiple supply voltages are supplied is extracted (Step S ), the extracted cells are divided into groups (Step S ), cells for voltage supply are added and arranged according to the number of the groups (Step S ), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S ).

SEMICONDUCTOR INTEGRATED CIRCUIT, SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT, AND RECORD MEDIUM FOR STORING PROGRAM OF SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT

A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed. The computer aided design for clock gated logic circuits is conducted by extracting, by the use of information about a clock gated logic circuit under the design, a halt condition under which a clocked circuit driven by a clock signal can halt with no clock signal supplied, generating enable signal candidates, from a halt condition, which can be used as enable signals in the clock gated logic circuit, analyzing the clock gated logic circuit in order to obtain information about a delay time of signal transmission and electric power consumption reduction if respective one of enable signal candidates is used as an enable signal of a clock gating circuit inserted in the clock gated logic circuit under the design, storing enable signal candidate information including the result of the analysis conducted by an analysis step in an information store, selecting an appropriate one of the enable signal candidates which satisfy given restrictions regarding a delay time of signal transmission in the clock gated logic circuit under the design, by the use of enable signal candidate information; and adding the clock gating circuit activated with the enable signal as selected by enable signal selection step to the clock gated logic circuit under the design.

Clock supplying circuit and method having enable buffer cells with first and second input terminals

Semiconductor circuit having a combination circuit being switched between an active and inactive state

A semiconductor integrated circuit has a CPU for executing various processes, at least one hardware module for receiving instructions from the CPU and executing the instructions, and a power management device for controlling the supply of a clock signal to the CPU so as to stop the clock signal to the CPU if the CPU has an idle time to start the next process. The power management device stops the supply of the clock signal to the CPU during a period in which the CPU can sleep, thereby reducing the power consumption of the CPU.

Semiconductor integrated circuit employing power management device and power management method for the semiconductor integrated circuit

Growing community of inventors

Kanagawa-ken, Japan

Kimiyoshi Usami