Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Kimio Ooe

Nobutaka Amano

Katsuaki Takagi

Takashige Kubo

Tetsuro Honmura

Kaoru Moriwaki

Shunpei Kawasaki

An address translation apparatus which includes a memory for storing a plurality of physical addresses, and a content addressable memory unit which stores a plurality of signal pairs that correspond to the plurality of physical addresses, each of the signal paris includes a logical address that corresponds to one of the plurality of physical addresses and memory protection level data that indicates a memory protection level allocated to a memory position of the one of the physical addresses. The content addressable memory unit includes apparatus for searching a signal pair that has a logical address in coincident with a logical address being subjected to address translation and comparing memory protection level data to comparative data at a bit position which is indicated to be the bit position to be searched by mask data, in response to the logical address translation. The mask data instructs whether the bits of the stored memory protection level data are to be searched, wherein mask data is determined depending upon a memory access privilege level allocated to a program that requests address translation, and whether comparative data are to be compared with the stored memory protection level data. The content addressable memory further includes apparatus for instructing the memory to produce a physical address that corresponds to the detected signal pair.

Address translation apparatus having a memory access privilege check

In a logic simulation method for performing logic simulation of a logic circuit including a circuit with unknown internal logic, the circuit itself with the unknown internal logic is used. The internal status of the circuit is set at an objective status using the interrupt operation afforded by the circuit and thereafter, input signal value is applied to the circuit to obtain a resultant output. For other logic circuits without unknown internal logic, software logic simulation is performed. During such software logic simulation, the actual circuit with unknown internal logic is called.

Logic simulation

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Kawasaki, Japan

Kimio Ooe