Pioneer Corporation

Pioneer Electronic Corporation

Other

Pioneer Electronics Corporation

Pioneer Display Products Corporation

Shizuoka Pioneer Corporation

Pioneer Display Corporation

Poineer Electric Corporation

Kimio Amemiya

Chiharu Koshio

Hitoshi Taniguchi

Tatsuro Sakai

Toshihiro Komaki

Kosuke Masuda

Tsutomu Tokunaga

Yasuhiro Torisaki

Nobuhiko Saegusa

Mario Amatsuchi

Hiroyuki Ajiki

Mitsunori Nozu

Eishiro Otani

Yoichi Sato

Kohsuke Masuda

Yukio Tanaka

Hitoshi Teshirogi

Shin Matsuda

Sota Okamoto

Hiroshi Adachihara

A plasma display panel comprises a front substrate and a rear substrate, a plurality of row electrode pairs provided on the inner surface of the front substrate, a dielectric layer provided on the inner surface of the front substrate for coverring the row electrode pairs, a plurality of column electrodes provided on the inner surface of the rear substrate, a partition wall assembly provided between the front substrate and the rear substrate, said partition wall assembly including a plurality of longitudinal partition walls and a plurality of lateral partition walls, forming a plurality of discharge cells. In particular, the dielectric layer has a plurality of projection portions located corresponding to and protruding toward the lateral partition walls of the partition wall assembly, in a manner such that there would be no slots formed between the dielectric layer and the lateral partition walls.

Plasma display panel

A display panel device includes a plurality of row electrode pairs and a plurality of column electrodes. Each row electrode pair includes a first and second electrodes. Unit light emission areas are formed at intersections of the row electrode pairs and the column electrodes. Each unit light emission area includes a first discharge cell and a second discharge cell. The second discharge cell includes a light-absorbing layer and secondary electron emission material layer. When driving the display panel device, sustain discharge responsible for light emission governing the display image is induced in the first discharge cells, whereas reset discharge and address discharge accompanied by light emission not contributing to the display image is induced in the second discharge cells.

Display device, and display panel driving method

An object of the present invention is to provide a high definition PDP screen without lowering the PDP luminescence efficiency. The display panel is provided with a plurality of cells that are arranged in a matrix, each of the plurality of cells emitting a different unique luminescent color; wherein a plurality of cells each bearing first luminescent color are disposed on every other line in a vertical direction, and a line of cells each having second luminescent color and a line of cells each having third luminescent color are alternated with a line of said plurality of cells having first luminescent color respectively therebetween.

Display panel and scanning method

A plasma display panel includes: a plurality of row electrode pairs (X, Y) provided on a front glass substrate (); a protective layer () on the front glass substrate (); and a plurality of column electrodes (D) provided in a back substrate () at intersections with the row electrode pairs (X, Y) to form discharge cells (C) in the discharge space (S). An ultraviolet region light emissive layer () having persistence characteristics allowing continuous emission of ultraviolet light as a result of excitation by ultraviolet rays having 0.1 msec or more of a wavelength is provided at a site facing each discharge cell (C) between the front glass substrate () and the back glass substrate ().

Plasma display panel that inhibits false discharge

A plasma display panel comprises a plurality of row electrode pairs (X, Y) provided on a front glass substrate , a plurality of column electrodes D provided on a back glass substrate and each intersecting the row electrode pairs, and discharge cells C which are defined in a discharge space S to correspond to the respective intersections. The row electrode Y of each row electrode pair (X, Y) has transparent electrodes Ya each constructed by a leading member Ya and a base member Ya . The column electrode D is provided with enlargement members Da, having a width in a row direction larger than that of the base member Ya , in a position opposite to the leading member Ya

Each of partition walls comprises vertical walls each positioned between adjacent discharge cells C in the row direction and extending in the column direction to form a partition between the adjacent discharge cells C and transverse walls bridging the vertical walls to define a top and bottom edge of the discharge cells C Each of the transverse walls of the partition wall is provided in a shape that its central part j located midway between adjacent vertical walls protrudes beyond its part j coupled to the vertical wall toward the outside of the discharge cell C in the column direction.

A plasma display panel includes a front glass substrate having the back surface on which a plurality of pairs of row electrodes X Y are formed, a back glass substrate on which column electrodes D are formed, and partition walls made of dielectric materials and defining individual discharge cells C, in which at least either of the row electrodes X and Y is placed at a position shifted relatively in the column direction toward decreasing the overlapping of the row electrode and the partition wall in reference to the partition wall

A plasma display panel includes a plurality of row electrode pairs (X, Y) forming display lines which are formed on a front glass substrate ( ). Each row electrode (X, Y) of the row electrode pair (X, Y) makes up transparent electrodes (Xa, Ya) each formed opposing the corresponding transparent electrode (Xa, Ya) via a discharge gap (g) for each pair, and a bus electrode (Xb, Yb) connected to the transparent electrodes (Xa, Ya). In such plasma display panel, a light-shield layer A is formed at least on a portion between the two bus electrodes situated back to back and a required portion in proximal to sides of the bus electrodes (Xb, Yb) connected to the transparent electrodes (Xa, Ya) on the front glass substrate ( ).

Plasma display panel and method of manufacturing the same

Each of partition walls of a plasma display panel has a pair of transverse walls which are disposed in parallel with each other having a space equal to a width of a discharge cell in the column direction, and vertical walls which are disposed between the pair of vertical walls in parallel with each other having a space equal to a width of the discharge cell in the row direction and which are integrally coupled to the pair of transverse walls. Each partition wall defines discharge cells in each line of the plasma display panel, and is formed such that a width of a portion of the transverse wall situated between the adjacent vertical walls is larger than a width of a portion of the transverse wall coupled to the vertical wall.

Partition-wall structure for plasma display panel

Row electrodes X, Y have bus electrodes Xb, Yb extending in the row direction and a plurality of transparent electrodes Xa, Xa&prime;, Ya, Ya&prime; extending in the column direction, arranged along the bus electrodes Xb, Yb and connected to the bus electrodes Xb, Yb with intersecting. Each end of the transparent electrodes Xa, Xa&prime;, Ya, Ya&prime; of one of the row electrodes X, Y and each end of the corresponding transparent electrodes Xa, Xa&prime;, Ya, Ya&prime; of the other are opposed to each other with a discharge gap g in between. Discharge cells C, C&prime; are formed in a discharge space between a front glass substrate and a back glass substrate , opposing the transparent electrodes Xa, Xa&prime;, Ya, Ya&prime;, which form pairs by opposing each other.

A plasma display panel is provided with discharge cells CB, CG, CR at intersecting positions of row electrode pairs (X, Y) formed on a front glass substrate 10 and column electrodes D formed on a back glass substrate 13, and formed with phosphor layers 16B, 16G, 16R of the three primary colors of red, green and blue in the discharge cells CB, CG, CR in order. In such plasma display panel, the discharge cell CR formed with a red phosphor layer 16R, the discharge cell CG formed with a green phosphor layer 16G and the discharge cell CB formed with a blue phosphor layer 16B respectively have opening areas SB, SG, SR opening toward the front glass substrate 10, which are set to be increased with decreasing order of luminance in accordance with each luminance of red, green and blue colors.

An additional dielectric layer ( A) is formed on a backside of a dielectric layer ( ) to protrude to the inside of a discharge space (S) and extend along an edge of a discharge cell C in parallel to the row direction. Row electrodes (X, Y) respectively have bus electrodes (Xb, Yb) extending along the edge of the discharge cells (C) in the row direction, and transparent electrodes (Xa, Ya) paired with each other in each discharge cell C. An overlap portion (m) of a proximal end (Xa , Ya ) of each transparent electrode (Xa, Ya) connected to the bus electrode (Xb, Yb), which overlaps the additional dielectric layer ( A), is designed to be smaller in width than that of a linking portion (Xa , Ya ) between the overlapping portion (m) and a distal end of the transparent electrode.

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Yamanashi-ken, Japan

Kimio Amemiya