Nec Corporation

Other

Ps4 Luxco S.a.r.l.

Kiminori Hayano

Hiroshi Furuta

Yasuhiro Maeda

Yoko Hayashida

A semiconductor device comprises a first power supply system, a second power supply system, an output circuit, a first driving circuit and a first protection. The first power supply system is configured with a first power supply voltage and a first ground voltage. The second power supply system is configured with a second power supply voltage and a second ground voltage. The output circuit receives a power supply from the second power supply system. The first driving circuit receives a power supply from the first power supply system and outputs a signal for driving the output circuit. One end of the first protection element is connected to an output node of the output circuit and the other end is connected to the first ground voltage.

Semiconductor device

A semiconductor device comprises a vertical MOS transistor including a semiconductor substrate having a silicon pillar, a gate electrode formed along a sidewall of the silicon pillar, a gate insulating film formed between the gate electrode and the silicon pillar, an upper diffusion layer formed on the top of the silicon pillar, and a lower diffusion layer formed lower than the upper diffusion layer in the semiconductor substrate; and a pad electrically connected to the lower diffusion layer. Breakdown occurs between the lower diffusion layer and the semiconductor substrate when a surge voltage is applied.

A semiconductor integrated circuit device is disclosed that can provide greater flexibility of layout while essentially ensuring circuit characteristics, and at the same time providing an minimum electrostatic discharge breakdown withstand value according to Charged Device Model (CDM) at all input/output (I/O) terminals. For each I/O terminal a size of a CDM protective device can be optimized in response to reference electric potential wiring resistance between an input protective device, a MOSFETs that can constitute an internal circuit, and an input resistance.

Semiconductor integrated circuit device and method for designing the same

To fabricate a smaller memory system, a memory system includes a memory cell array having a first memory cell and a second memory cell, a first switching circuit connected to the first memory cell, a second switching circuit connected to the second memory cell, and a sense amplifier connected to the first and second switching circuits. The sense amplifier includes an N-type flip-flop circuit for selectively amplifying data from the first memory cell or the second memory cell, a P-type flip-flop circuit for selectively amplifying the data from the first memory cell or the second memory cell, and a first circuit formed between the N-type flip-flop circuit and the P-type flip-flop circuit. When data in the first memory cell is to be transferred, the first switching circuit is activated and the data from the first memory cell is transferred to the sense amplifier, and then the data is amplified by the sense amplifier. When data in the second memory cell is to be transferred, the second switching circuit is activated and the data from the second memory cell is transferred to the sense amplifier, and then the data is amplified by the sense amplifier.

Single-chip memory system and method for operating the same

A semiconductor memory device has a memory cell area and a peripheral area including a scribe area. A large number of first monitoring patterns are disposed in the scribe area for monitoring the peripheral circuit in the peripheral area, whereas a few number of second monitoring patterns are disposed adjacent to the memory cell area for monitoring the characteristics of the memory cells. A CMP process which reduces the thickness of the memory device does not generate dust of the conductive material from the scribe area because the first monitoring pattern has a level substantially equal to the level of the peripheral area.

Semiconductor memory device having a monitoring pattern

A semiconductor device has a semiconductor chip which is divided into a plurality of separate regions. In each of these regions, there are provided a plurality of common discharge lines which are independent from one another, a plurality of first bonding pads which are connected directly to the respective common discharge lines, a plurality of second bonding pads which are not connected directly to the common discharge lines, a plurality of protective elements which are connected between the second bonding pads and the common discharge lines, and an inner lead for discharging which is directly connected to the first bonding pads and is bonded to a surface of the semiconductor chip. In all embodiments of the invention. More than one common discharge line is provided. This arrangement permits the reduction of the chip area thus enhancing design freedom and improving electrostatic breakdown characteristics.

Semiconductor device equipped with electrostatic breakdown protection

A dynamic random access memory device has a plurality of sense amplifier circuits shared between two regular memory cell arrays respectively associated with redundant memory cell arrays, and two transfer gate arrays are coupled between one of the regular memory cell arrays and one of the redundant memory cell arrays as well as between the other regular memory cell array and the other redundant memory cell array so that a large number of defective memory cells are replaceable with both of the redundant memory cell arrays, thereby improving production yield.

Dynamic random access memory device with redundant word lines shared

A boundary region for wiring is provided by expanding one of a plurality of boundary regions boundary regions each being between adjacent ones of a plurality of decoder circuits included in a decoder circuit block corresponding to a memory cell array by shifting a desired portion of at least one of the decoder circuits by a desired distance and a wiring connecting wirings in the decoder circuit to a circuit provided outside the decoder circuit block is arranged in the boundary region for wiring, so that a circuit arrangement in a second region outside the decoder circuits can be made freely.

Semiconductor memory device wired to accommodate increased capacity

A MOS type semiconductor device forming an insulated gate field effect transistor and a potential stabilizing circuit connected between power voltage supply lines is disclosed. The potential stabilizing circuit includes first and second MOS type capacitors connected in series each other, and the dielectric film of each of the MOS type capacitors has the same thickness and is made of the same material as the gate insulating film of the transistor.

Growing community of inventors

Tokyo, Japan

Kiminori Hayano