Toyota Jidosha Kabushiki Kaisha

Denso Corporation

Kimimori Hamada

Hidefumi Takaya

Norihito Tokura

Akira Kuroyanagi

Jun Saito

Sachiko Aoi

Akitaka Soeno

Yuji Nishibe

Yasushi Okura

Kyosuke Miyagi

Yukihiko Watanabe

Toshimasa Yamamoto

Shoji Mizuno

A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.

Semiconductor device and method of manufacturing semiconductor device

An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches.

Insulated gate type semiconductor device

Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: 

Semiconductor device

Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current. In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: 

The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.

Insulated gate semiconductor device and method for producing the same

A semiconductor 100 has a Pbody region and an Ndrift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the Pbody region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A Pdiffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the Pbody region and the P diffusion region, is formed. The Pdiffusion region is depleted prior to the P diffusion region when the gate voltage is off. The Pdiffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.

Insulated gate-type semiconductor device having a low concentration diffusion region

The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region, N+ drain regionP&#x2212; body regionand N&#x2212; drift regionBy excavating part of the upper side of the semiconductor device, a gate trenchis formed. The gate trenchincorporates the gate electrode. A P floating regionis provided beneath the gate trenchA further trenchdiffering in depth from the gate trenchmay be formed, a P floating regionbeing provided beneath the trench

Insulated gate type semiconductor device and manufacturing method thereof

A power semiconductor device having a low on-resistance and a high breakdown ruggedness is disclosed. Trench regions formed so as to contact trench gates via gate-insulating films are connected by emitter regions so as to form a ladder-shaped configuration. The emitter regions are formed at a shallower depth than the trench regions. Therefore, the resistance in portions of the body that are near the interfaces with the emitter regions is reduced, and the operation of parasitic transistors formed by the emitter regions, the body, and an epitaxial layer is substantially prevented. As a result, the on-resistance is varied, and the avalanche ruggedness and the latch-up ruggedness are improved.

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Toyota, Japan

Kimimori Hamada