Sony Corporation

Kimimasa Senba

Norio Shoji

Junkichi Sugita

Masayuki Katakura

Nobuyoshi Kobayashi

Yuji Gendai

Katsuhisa Daio

Kenichi Ishida

Toshihiro Kawakubo

Masato Sekine

Shinya Nouchi

Disclosed herein is a misjudgment correction circuit, including, an edge detection section configured to detect, in a binarized full addition signal obtained by adding first and second signals of the same or opposite polarity, edges at which the logic value of the binarized signal changes, a push-pull signal acquisition section configured to acquire a binarized push-pull signal obtained by subtracting the second signal from the first signal, a majority decision calculation section configured to acquire, in chronologic order, a plurality of logic values of the push-pull signal between the two adjacent edges so as to determine, by a majority decision, the more numerous of the two logic values, and a wave correction section configured to correct the push-pull signal between the edges to the more numerous logic value determined by the majority decision calculation section.

Misjudgment correction circuit and optical disk drive

A comparator includes a variable-gain amplifier circuit configured to vary an amplitude of an input signal by changing a gain in accordance with a control signal, and a comparison section configured to compare a slice level interlocked with a signal level received from the variable-gain amplifier circuit with an output signal received from the variable-gain amplifier circuit and generate an output signal in accordance with a comparison result.

Comparator and optical-disc recording/reproduction apparatus

A wobble signal extraction circuit includes: an RF signal component acquiring portion for acquiring an RF signal component from at least one of first and second signals received by two light receiving portions, the two light receiving portions being obtained through division in halves with a direction along which each track of an optical recording medium extends as a boundary; a wobble signal acquiring portion for acquiring a wobble signal by subtracting the second signal from the first signal; an RF signal component binarizing portion for binarizing the RF signal component; a wobble signal binarizing portion for binarizing the wobble signal; and an exclusive OR arithmetically operating portion for arithmetically operating an exclusive OR of the binarized RF signal component and the binarized wobble signal; wherein balances between amplitudes of the first and second signals are detected based on an arithmetic operation result obtained in the exclusive OR arithmetically operating portion.

Wobble signal extraction circuit and optical disk device

A PLL circuit functioning as a clock recovery circuit in a tape recording and playback apparatus employing the PRML method has a level determining circuit for detecting that head output level (signal level) is at or lower than a certain level during track crossing for a high-speed search, and effects a hold on a loop filter according to a level determination output to thereby hold PLL operation, whereby the PLL behavior is not disturbed by a noise component occurring during track crossing. Thus, it is possible to stabilize search operation and increase the design margin.

PLL circuit and recording and playback apparatus using same

To provide an asymmetry correcting circuit capable of canceling an asymmetry simultaneously with quantization in an ADC and utilizing the dynamic range of the ADC effectively, and also to provide an information reproducing apparatus using such a correcting circuit. An asymmetry correcting circuit includes a first envelope detection circuit for detecting the envelope of a positive peak of an input signal waveform; a second envelope detection circuit for detecting the envelope of a negative peak of the input signal waveform; an adding circuit for producing a sum voltage of the positive peak voltage and the negative peak voltage; a smoothing circuit for smoothing the sum voltage; a multiplying circuit for multiplying the smoothed sum voltage by a predetermined offset adjustment coefficient; and a quantization reference voltage control circuit for DC-wise shifting, in response to the output signal of the multiplying circuit, the median of the quantization reference voltage of the ADC in conformity with the offset derived from the asymmetry of the input signal, and controlling the upper limit and the lower limit of the quantization reference voltage to the values that correspond to the offset quantity.

Asymmetry correcting circuit and information reproducing apparatus using the same

A nonlinearity compensation circuit is disclosed which includes an inverse hyperbolic function generation circuit for converting differential currents corresponding to input signals in&plus; and in&minus; into differential voltages which increase in proportion to an inverse hyperbolic function, an offset provision circuit for providing an offset corresponding to control signals c&plus; and c&minus; to the differential voltages outputted from the inverse hyperbolic function generation circuit and a hyperbolic function generation circuit for converting the differential voltages to which the offset has been provided by the offset provision circuit into signals which increase in proportion to a hyperbolic function and outputting the resulting signals as output signals out&plus; and out&minus;. Consequently, compensation for the nonlinearity such as second order distortion can be performed for the read signal from a recording medium.

Nonlinearity compensation circuit and method, control circuit and method for nonlinearity compenstation circuit and recording and/or playback apparatus employing the same

A PLL (phase-locked loop) circuit is configured with a phase-error detection circuit comprises the following: a provisional judge circuit for provisionally judging a data signal being input to an A/D converter into three levels of , and &minus; ; a pattern detector which, among data signals being input in accordance with a result of the provisional judgment, checks a transition pattern ranging from a data signal that precedes one clock cycle to the actually present data signal, and then, when a specific pattern is detected, instructs a selector to select output data from the A/D converter; and the selector which, in compliance with instruction from the pattern detector, selects phase-error data from data signals output from the A/D converter, and then converts the selected phase-error data into an electric current before externally delivering it as an error-current.

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Kanagawa, Japan

Kimimasa Senba