Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Kimihiro Sugino

Mitsumasa Satoh

In the digital signal processor used for realizing application filters, the filter output calculation processing system 5 and the tap coefficient update calculation processing system 6 are separated. In the update calculation processing system 6, the integrating calculation for the tap coefficient updating that requires read and write operations on the data memory DRM is performed in one machine cycle by using the dedicated data bus 10 and executing the read-modify-write operation on the data memory. As a result, to the extent that the time taken by the integrating processing which has conventionally required two machine cycles can be shortened, the operation clock frequency can be lowered to reduce the power consumption while maintaining the processing capability per unit of time.

Arithmetic circuit, and adaptive filter and echo canceler using it

An A/D converter included in an echo canceller or the like is furnished with a plurality of rate changing filters that receive the output signals of an oversampling A/D conversion circuit in common, the integration phases of the filters are different from each other as they are selectively advanced or retarded for each one of a plurality of predetermined intervals, and further furnished with an output selection circuit by which internal digital signals delivered as outputs from one of the rate changing filters are selectively transmitted according to the desired phase change.

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Ohme, Japan

Kimihiro Sugino