Oki Electric Industry Co., Ltd.

Oki Semiconductor Co., Ltd.

Kimiaki Shimokawa

Takashi Usami

Masaki Yoshimaru

Shuichi Noda

Hiroshi Hoga

The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side.

Method for manufacturing silicon on sapphire wafer

The present invention includes a substrate structural body having a high electrostatic chuck force at a low voltage even when an insulated board is used, and a method for manufacturing the substrate structural body. As the substrate structural body, there is provided a substrate structural body for attaining its fixing by an electrostatic chuck mechanism, comprising at least a first polycrystalline silicon film formed on the back surface of a substrate comprised of an insulating material or its back and side surfaces, wherein a top layer of part of the back surface or the back and side surfaces is of a first silicon insulating film.

Structural body and manufacturing method thereof

Silicon on sapphire wafer

The polishing particle surface of the dresser of a chemical mechanical polishing apparatus used for a planarization process in manufacturing semiconductor devices is inclined. Moreover, the pressure to be applied onto the polishing surface of the dresser is linearly varied with a nonzero slope.

Polishing apparatus having a dresser and dresser adjusting method

A polishing pad is conditioned using a conditioning disc whose temperature is controlled upon Chemical Mechanical Polish. The temperature of the polishing pad remains unchanged upon conditioning and uniform CMP can be carried out.

Method and apparatus for polishing wafer

A method for manufacturing an inter-layer insulating film (ex. O.sub.3, TEOS or NSG) with a superior surface flatness is disclosed to solve the problem that the surface of the inter-layer film formed on a certain under-layer substrate reveals roughness due to the influence of the substrate. It is provided a method for manufacturing O.sub.3 TEOS NSG film after doping nitrogen (N) atoms into the under-layer films, or after forming the under-layer films which contain nitrogen (N) atoms therein.

Method for manufacturing an inter-layer insulating film

An insulating film formed under a conductive film has a side wall defining a contact window and having the shape of a gently inclined curvilinear surface, so that the insulating film is able to provide a sufficient step coverage in the contact window. The insulating film is formed over the surface of a semiconductor substrate or a first conductive film. The insulating film has an increasing or decreasing refractive index over the depth thereof. A contact window is formed by selectively removing a portion of the insulating film using a photoresist pattern formed over the surface of the insulating film. A structure thus formed is subjected to an etching process capable of etching the upper layer of the insulating film at an etching rate higher than that for the lower layer of the same to etch the side wall of the insulating film defining the contact window into a gently inclined curvilinear surface, and then the photoresist pattern is removed. A second conductive film is formed over the surface of a structure formed in the preceding step.

Growing community of inventors

Tokyo, Japan

Kimiaki Shimokawa