Cascade Microtech, Inc.

Triquint Semiconductor Corporation

Kimberly R Gleason

Eric W Strid

William A Vetanen

Irene G Beers

Jeremy N Burr

Larry R Lockwood

Robert T Flegal

Angus J McCamant

Gregory Nordgren

A shielded microwave probe tip assembly includes an end of a coaxial cable coupled to probe fingers forming a coplanar controlled impedance microwave transmission line where the ground probe fingers are interconnected by a shield member that is spaced apart from the signal line probe finger but is positioned between the signal line probe finger and a device under test. The shield prevents the generation of extraneous signals or parasitic coupling from the device under test which would otherwise degrade measurement accuracy.

Coaxial wafer probe with tip shielding

A wafer probe comprises a support member having an end region which is shaped to permit the end region to be brought into close proximity with a component under test. An amplifier is mounted on the support member at its end region. A conductive probe element is attached to the amplifier and is electrically connected to the amplifier's input terminal. A transmission line is connected to the amplifier's output terminal for transmitting signals from the amplifier to a measurement instrument.

Wafer probes

A wafer probe for accessing bonding pads on a planar device includes contact pads mounted on one edge of the under side of a dielectric substrate board and arranged to align with the bonding pads to be accessed. Coplanar ground and signal conductors deposited on the under side of the substrate board form constant impedance transmission lines for connecting test equipment to the contact pads. A ground contact is mounted on the upper side of the substrate near the end on which the contact pads are mounted, the ground contact being connected by a conductive path to the ground conductors on the under side of the substrate. When two such wafer probes simultaneously access bonding pads on the same planar device, the ground conductors of the two probes are interconnected by a conductive sheet of foil extending between the ground contacts on the upper sides of the substrates of both wafer probes.

Wafer probe

A wafer probe is provided having metallic transmission lines mounted on a tapered alumina substrate generally surrounded by microwave absorbing material. The probe provides for on-wafer measurements of small planar devices at frequencies from DC to at least 18 GHz with low inductance, and with constant characteristic impedance from the probe external cable terminal to the point of contact on device being probed. The microwave absorbing material absorbs energy propagating along the probe ground preventing this energy from resonating, radiating and re-exciting normal transmission line modes with minimal transmission line mode resonance along the probe ground. The probe, which may be coupled to receive signals from a coaxial cable, is capable of making contact with bonding pads of a device having a center-to-center distance between pads of only 4 mils.

An integrated circuit gate process and structure are disclosed which provide a self-aligned, recessed gate enhancement-mode GaAsFET. The process includes making self-aligned implants prior to gate metallization, with an intermediate step of applying patches of plasma- and chemical-etch resistant dielectric, such as zirconium oxide (ZrO), over the self-aligned implants to fixedly define gate length. The self-aligned gate process includes stair-stepping three successive implants, in respect to both depth and concentration, to provide a dopant concentration gradient inclined depthwise away from each side of the gate. The self-aligned, recessed gate GaAsFET exhibits improved source-gate resistance without degradation of gate-drain capacitance, increased gain and drain-source current, and reduced knee-voltage. Gate length is minimized to the limits of photolithography without degrading input resistance.

Self-aligned recessed gate process

A self-aligned gate GaAsFET fabrication process and structure are disclosed in which the gate metallization is offset to one side of the channel aligned with the source-side implant. The arrangement is advantageously provided by a photolithographic fabrication process in which a pair of self-aligned implants are made, before gate metallization. As an intermediate step, a first etch-resistant ZrO patch is deposited over at least one of the self-aligned implants aligned therewith. Then, a second such patch is deposited which overlaps the other self-aligned implant and extend a distance over the channel between the two implants. The first and second patches are thereby spaced closer together (e.g., 0.5 .mu.m) than the implants (e.g., 1.0 .mu.m). The patches fix the gate length at less than implant spacing and offset the gate metallization along the source-side self-aligned implant, away from the drain implant. The gate is preferably recessed. This arrangement effectively provides asymmetrical doping concentrations on opposite sides of the gate conductor, which enables improvement in both gate-drain capacitance C.sub.gd and source-gate resistance R.sub.s.

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Portland, OR, United States of America

Kimberly R Gleason