Intel Corporation

Kimberly C Weier

Jason W Brandt

Matthew C Merten

Ahmad Yasin

Seth Abraham

Michael W Chynoweth

Angela D Schmid

Beeman C Strong

Andreas Kleen

Stanislav Viktorovich Bratanov

Grant G Zhou

Krishnakanth Venkata Sistla

Alexander Gendler

Stephen S Pawlowski

Vivek Garg

Dean A Mulla

Ashish V Choubal

Jonathan D Combs

Larisa Novakovsky

Erik Hallnor

Daniel G Lau

Charlie J Hewett

Erik G Hallnor

A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.

Virtualizing precise event based sampling

A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as trace data packets. An event-based sampler generates field data for a sampling record in response to occurrence of an event of a certain type as a result of execution of the instruction. The processor tracer, upon receipt of the field data: formats the field data into elements of the sampling record as a group of record packets; inserts the group of record packets between the trace data packets as a combined packet stream; and stores the combined packet stream in the memory buffer as a series of output pages. The core, when in guest profiling mode, executes a virtual machine monitor to map output pages of the memory buffer to host physical pages of main memory using multilevel page tables.

In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.

Masking a power state of a core of a processor

A processor and method are described for implementing performance monitoring using a fixed function performance counter. For example, one embodiment of an apparatus comprises: a fixed function performance counter to decrement or increment upon occurrence of an event in the processing device; a precise event based sampling (PEBS) enable control communicably coupled to the fixed function performance counter; a PEBS handler to generate and store a PEBS record comprising architectural metadata defining a state of the processing device at a time of generation of the PEBS record; and a non-precise event based sampling (NPEBS) module communicably coupled to the PEBS enable control and the PEBS handler, the NPEBS module to cause the PEBS handler to generate the PEBS record for the event upon the fixed function performance counter reaching a specified value.

Method and apparatus for processor performance monitoring

In one embodiment, the invention includes an apparatus, such as a bridge, for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus a task priority update transaction including data representative of a task priority designation of a processor of the computer system, and to provide a signal responsive thereto. The apparatus also includes remote priority capture logic to receive the signal responsive to the task priority update transaction and update contents of the remote priority capture logic in response thereto. In another embodiment, the invention includes an apparatus for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus an end-of-interrupt (EOI) transactions and to provide an EOI signal responsive thereto. The apparatus also includes an interrupt controller including a table having a state bit that is set in response to the interrupt controller receiving an interrupt signal and reset in response to the interrupt controller receiving the EOI signal.

Transactions supporting interrupt destination redirection and level triggered interrupt semantics

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Austin, TX, United States of America

Kimberly C Weier