Telairity Semiconductor, Inc.

Kim R Stevens

John Gray Campbell

Luigi DiGregorio

Techniques are provided for reducing the power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to solder bumps that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage Vand a low power supply voltage V. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.

Power grid layout techniques on integrated circuits

Techniques are provided for reducing power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to bond pads that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage Vand a low power supply voltage V. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.

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Santa Clara, CA, United States of America

Kim R Stevens