Intel Corporation

Kim R Kokkonen

Alan C Folmsbee

William J Spaw

Richard D Pashley

William H Owen, Iii

An improved addressing means for single chip memories which include a plurality of redundant lines and associated cells is described. Y address signals are used during programming to select and program redundant X decoders. The redundancy apparatus is implemented without any additional package pins and programming may be performed after packaging. The apparatus includes means for permanently disabling further programming of the redundancy circuitry to prevent inadvertent programming by a user.

Memory redundancy apparatus for single chip memories

An improved addressing means for single chip memories which include a plurality of redundant lines and associated cells is described. Y address signals are used during programming to select and program redundant X decoders. The redundancy apparatus is implemented without any additional package pins and programming may be performed after packaging. The apparatus includes means for permanently disabling all further programming of the redundancy circuitry to prevent inadvertent programming by a user.

An integrated circuit, metal-oxide-semiconductor (MOS) static random-access memory (RAM) with a power-down mode is described. The bistable memory cells employed in the memory include low conductivity, depletion mode transistors used as loads. 'Zero' threshold voltage devices are employed on a low body-effect substrate to permit the powering-down of many circuits in the memory without affecting circuit performance. Several circuits employing these zero threshold devices are described.

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Sunnyvale, CA, United States of America

Kim R Kokkonen