Virage Logic Corporation

Kim-Kwong Michael Han

Narbeh Derhacobian

Jaroslav Raszka

A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.

Electrically-alterable non-volatile memory cell

A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N&plus; doped material and P&plus; doped material, and a P&plus; doped region abutted to a N&plus; doped region. The P&plus; doped region abutted to the N&plus; doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N&plus; doped material and P&plus; doped material.

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Los Gatos, CA, United States of America

Kim-Kwong Michael Han