Motorola Corporation

Kim H Eckert

John E Zolnowsky

Douglas B MacGregor

Ken Ota

Richard DeWitt Crisp

William C Archibald

Craig A Cavins

James S Thomas

Lam Ta

An EEPROM cell (32) is formed having a vertical select gate (34) and a horizontal select gate (40). The vertical select gate (34) and the horizontal select gate (40) enable two dimensional decoding which selects which one or which plurality of memory cells (32) are enabled for program, erase and read operations. An additional select gate having a control electrode (44) can be added to the cell (32) to provide additional decoding as is necessary. This split gate EEPROM cell (32) can be readily integrated onto an integrated circuit which also contains flash memory (204). The flash memory (204) and the split control gate EEPROM array (202) can share the same common charge pumps circuit (208).

Split-Control gate electrically erasable programmable read only memory

A data processor processes input data using fuzzy logic operations. The input data consists of n-bits (where n is a natural number greater than 2) and appears at a rate of .function.. The data processor outputs the processed data at a given number of bits and a given rate. The data processor includes a first converter (10), a fuzzy computing element (20), and a second converter (30). The first converter converts the input data into converted data consisting of m bits (where m is a natural number less than n and appearing at a rate of (2.sup.n-m).function.. The fuzzy computing element performs fuzzy logic operations on the converted data and sends the processed data to the second converter. The second converter converts the process converts the process data into output data at the given rate and with the given number of bits.

Fuzzy logic data processor

An asynchronous ripple counter counts from a predetermined binary value to zero in response to an input clock signal. Zero detection logic is coupled to the ripple counter for detecting, from a most significant bit to a least significant bit of the ripple counter, when the counter has counted to zero. Both the counter and the zero detection logic receive and store the predetermined binary value. The monitoring of the ripple counter's digits from MSB to LSB prevents false detections of zero states in the ripple counter and allows the ripple counter to be extended to an arbitrarily large number of bits without sacrificing the maximum input clock frequency.

Ripple counter with reverse-propagated zero detection

A pipelined data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. In response to detecting a particular sequence of a loopable instruction followed by a conditional branch instruction which selectively branches back to the loopable instruction, the data processor enters a loop mode wherein the loopable instruction and the branch instruction are internally recirculated around the pipeline to save instruction fetch cycles.

Data processor which can repeat the execution of instruction loops with

A three state output circuit which pulls down the output node thereof to a first supply voltage in response to an assert signal, pulls up the output node to a second supply voltage in response to a rescind signal, and then presents a high impedance on the output node immediately after the output node is pulled up to a selected reference voltage.

Three state output circuit

An N-channel MOS high voltage detection circuit generates an output when an input voltage (Vin) exceeds a supply voltage (V.sub.DD) by a desired offset voltage. The crossover detection is delayed by pumping more current into an output producing node via a lower resistance field effect transistor having a gate coupled to the input voltage. The output is finally produced when the effect of this transistor is overcome by a second field effect transistor. Switching characteristics may be sharpened by placing a voltage limiting field effect transistor between Vin and the gate of the low resistance field effect transistor.

High voltage detection circuit

A compensated Schmitt trigger includes first and second balanced current paths between V.sub.DD and ground for establishing the Schmitt trigger's low and high output respectively. The first path includes a first small enhancement device, a second depletion device and a third enhancement device. The second path includes a fourth enchancement device and said second and third devices. Thus, each path includes two enhancement devices and one depletion device. Process variations in each path will tend to track stabilizing the difference between the low and high switching voltages.

Schmitt trigger

An A.C. zero crossover detection circuit compensates for RC phase lead by adding hysteresis to the reference voltage. A reference voltage is applied directly to a first input of a differential amplifier and indirectly through first and second resistor connected field-effect-transistors to a second input of the differential amplifier. An output of the amplifier is coupled to the gate of an MOS switch which, when turned on, reduces the reference voltage by a predetermined amount to compensate for early crossover detection resulting from the phase lead.

Zero crossover detector

A differential amplifier, preferably comprised of N-channel MOS devices and having a high ratio of differential gain to common mode gain, has an input stage which receives first and second potentials and amplifies the difference therebetween. Additional amplifying stages each include a depletion input load device having a gate which is coupled to the second potential for balancing the switching points of each additional stage over the common mode range.

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Austin, TX, United States of America

Kim H Eckert