Intel Corporation

Kim Daehyun

Sara S Baghsorkhi

Victor W Lee

Tin-Fook Ngai

Jayashankar Bharadwaj

Albert Hartono

Nalini Vasudevan

An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.

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San Jose, CA, United States of America

Kim Daehyun