Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Kilhoon Lee

Hyunwook Lim

Kyungho Ryu

Jungpil Lim

Yong-Yun Park

Youngmin Choi

Kyongho Kim

Jung-Pil Lim

Jihee Park

Taeho Lee

Kyungae Kim

Keonwoo Kim

Younghwan Chang

Jihye Yoon

Nayeon Jung

Kiryong Jeong

Yeongcheol Rhee

Yongil Kwon

Jaeyoul Lee

Eun-young Jin

Hansu Pae

Sengsub Chun

Seng-Sub Chun

Youngseo Kim

Yongyun Park

A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

Clock and data recovery circuit and a display apparatus having the same

Disclosed is a display device. The display device according to an aspect of the present disclosure may include: a display panel; a frame which is positioned behind the display panel, and to which the display panel is coupled; a plurality of substrates which are positioned between the display panel and the frame, on which a plurality of light sources providing light to the display panel are mounted, and which are formed of flat plates separated from each other; and a reflective sheet positioned between the display panel and the plurality of substrates, covering the plurality of substrates, and having a plurality of holes corresponding to the plurality of light sources, wherein the plurality of substrates may include: a first substrate; a second substrate next to the first substrate; and a third substrate next to the second substrate, wherein the reflective sheet may include: a first reflective sheet covering at least a portion of the first substrate and a portion of the second substrate; and a second reflective sheet covering another portion of the second substrate and at least a portion of the third substrate.

Display device

Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes 'M' consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.

Electronic device and operating method of a decoder

A display device of the present disclosure includes: a display panel; a frame which is positioned in a rearward direction of the display panel, and to which the display panel is coupled; a substrate which is positioned between the display panel and the frame, and fixed to the frame; a plurality of light sources mounted on the substrate to form a row and a column; a reflective sheet which is positioned on the substrate, and has a plurality of holes through which each of the plurality of light sources passes; and a light pattern which is formed on the reflective sheet, and converts a color of a light provided by the plurality of light sources, wherein the reflective sheet includes: a first hole positioned adjacent to an edge of the reflective sheet; a second hole which is positioned adjacent to the first hole and positioned farther than the first hole from the edge of the reflective sheet; a first area positioned around the first hole; and a second area positioned around the second hole, wherein the light pattern includes: a first light pattern positioned in the first area; and a second light pattern positioned in the second area, wherein an area of the first light pattern is larger than an area of the second light pattern.

Display device with reflective sheet having color converting light patterns

The present disclosure provides methods and apparatuses for correcting skew. In some embodiments, a skew correcting device includes a plurality of samplers configured to sample first data based on a plurality of data clock signals with different phases, and a plurality of edge selectors configured to determine to switch at least one data clock signal of the plurality of data clock signals to an edge clock signal according to a sampling result of the plurality of samplers.

Semiconductor device and operating method thereof

Provided is a display driving circuit. The display driving circuit includes a clock data recovery circuit configured to receive a data signal and generate a clock signal and a first output data signal, an eye margin test circuit configured to sample the data signal by using the clock signal, based on a vertical measurement voltage and generate a second output data signal, and a bit error check circuit configured to measure a bit error rate of the data signal, based on the first output data signal and the second output data signal, wherein the clock data recovery circuit includes a jitter generator configured to generate jitter of the clock signal such that a jitter amplitude varies according to a horizontal control signal.

Display driving circuit, display device including the same, and method of operating the same

Encoder generating data packet, operation method thereof, and operation method of electronic device including encoder

An operation method of a receiver, which includes setting a coefficient of an equalizer based on one of a plurality of first codes, setting a coefficient of an amplifier based on one of a plurality of second codes, performing offset calibration by driving the equalizer and the amplifier based on the coefficient of the equalizer and the coefficient of the amplifier, storing an offset code corresponding to a voltage offset generated when the equalizer and the amplifier are driven, determining whether the offset calibration is completed, performing a normal operation of obtaining reception data from an input signal, in response to determining that the offset calibration is completed, and removing the voltage offset based on the offset code, in the normal operation.

Receiver for compensating for voltage offset in real time and operation method thereof

A receiver circuit includes an equalizer configured to generate an equalization signal by equalizing an input data signal transferred through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalization signal, generate a data sample signal including a plurality of data bits by sampling the equalization signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.

Receiver circuit performing adaptive equalization and system including the same

A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data, packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.

Growing community of inventors

Seoul, South Korea

Kilhoon Lee