Samsung Electronics Co., Ltd.

Kil-soo Kim

Kyung-suk Oh

Yong-hoon Kim

Won-keun Kim

Ji-Han Ko

Tae-joo Hwang

Yeong-seok Kim

Hwa-il Jin

Su-jung Hyung

Joung-phil Lee

Sun-Won Kang

Sun-Pil Youn

Joong-Hyun Baek

Hyun-ki Kim

Chul Won Park

Jin-Yang Lee

Chan-Min Han

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

Semiconductor package including processor chip and memory chip

An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.

Semiconductor device package

A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

Semiconductor packages having improved thermal discharge and electromagnetic shielding characteristics

Electronic device including semiconductor device package

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.

Semiconductor package

Provided is a semiconductor device having as many input/output pads as possible using a chip having a small number of input/output pads. The semiconductor device includes a substrate including first and second extending input/output pads, a first memory structure disposed on the substrate and including first connecting input/output pads, a second memory structure disposed on the first memory structure and including second connecting input/output pads, and a wiring structure formed on lateral surfaces of the first and second memory structures and connecting the first and second connecting input/output pads and the first and second extending input/output pads, respectively; wherein the wiring structure includes a first wiring connecting the first connecting input/output pads and the first extending input/output pad and a second wiring connecting the first connecting input/output pads and the second extending input/output pad, and the second wiring is offset relative to the first wiring.

Semiconductor device

A multi-chip package may include a package substrate, a connecting substrate, a plurality of semiconductor chips and a logic chip. The package substrate may have an opening. The connecting substrate may be arranged on an upper surface of the package substrate. The semiconductor chips may be stacked on an upper surface of the connecting substrate. The semiconductor chips may be electrically connected with the connecting substrate. The logic chip may be arranged in the opening. The logic chip may be electrically connected between the connecting substrate and the package substrate. Thus, the logic chip may not act as to increase a width of the multi-chip package.

Multi-chip package having a logic chip disposed in a package substrate opening and connecting to an interposer

A semiconductor package includes a semiconductor chip stack disposed between first and second leads near first and second sides of the package and including a plurality of semiconductor chips, and a redistribution structure disposed on the semiconductor chip stack. At least one semiconductor chip of the semiconductor chip stack includes a plurality of first chip pads disposed near or closer to a third side of the package. The redistribution structure includes a first redistribution pad disposed near or closer to the first side and electrically connected to the first lead, a second redistribution pad disposed near or closer to the second side and electrically connected to the second lead, and a third redistribution pad disposed near or closer to the third side and electrically connected to a first one of the first chip pads and the first redistribution pad.

Integrated circuit packages having redistribution structures

A multi-channel package has at least four channels and includes a package substrate having a first surface and a second surface, semiconductor chips mounted on the first surface of the package substrate, and external connection terminals disposed on the second surface of the package substrate and electrically connected to the semiconductor chips by the at least four channels. Each channel is dedicated to one or a group of the chips. An electronic system includes a main board, at least one such multi-channel package mounted on the main board, and a controller package that is mounted on the main board, has 4n channels (wherein n&#x2267;2) and controls the at least one multi-channel package.

Multi-channel package and electronic system including the same

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Growing community of inventors

Hwaseong-si, South Korea

Kil-soo Kim