Mitsubishi Denki Kabushiki Kaisha

Kikuo Muramatsu

Yasushi Okamoto

Akiya Arimoto

Norio Matsumoto

Osamu Ueda

Mitsuru Sugita

Toyokatsu Nakajima

Shigeo Mizugaki

Shinji Suda

Etsuya Yokoyama

Yoshikazu Satou

Yuichiro Yamaguchi

Takeshi Nita

A communication control apparatus, provided with an echo back comparison detecting unit (30) detecting something abnormal of communication data from itself or an abnormal state generated at a data line (4), by starting transmission of communication data from itself following a detection of a line state detecting unit (29), when the line state detecting unit (29) detects that transmission of communication data from another communication apparatus to a data line (4) is started in a transmission permissible section, and by taking in communication data at the data line (4) and by comparing it with communication data having been transmitted from itself, and further provided with a transmission mark generating unit (23) shortening a bit width of data indicating a start of communication data transmitted from itself, prevents an abnormal waveform from being transmitted to the data line (4) because accuracy of echo back comparison is improved and delay tolerance of the data line (4) is eased.

Communication control apparatus

A primary object is to provide a communication apparatus, in particular, its buffer memory which conforms mainly to specifications of SAE-J1850 or ISO-9141. In the buffer memory, there are provided: at least, one more status registers storing information associated with the state of respective information to be transmitted and received, than the number of buffers storing information to be transmitted and received; at least, the same number of transmission error registers storing information associated with the transmitting state of information to be transmitted, as the buffers storing information to be transmitted; at least, one more receiving error registers storing information associated with the receiving state of information to be received, than the buffers storing information to be received; at least, one more source address registers storing information associated with the other communication apparatus which has transmitted respective information to be received, than the buffers storing information to be received; and at least, the same number of response information registers storing information responded from the communication apparatus which is to receive information when the information to be transmitted is transmitted, as the buffers storing information to be transmitted.

Vehicle based LAN a communication buffer memory having at least one more

A multiprocessor system includes the first microcomputer (1) having the first memory (4); the second microcomputer (9) having the second memory (12), the dual port third memory (14), and an offset register (22); buses (18-20) for connecting the first and second microcomputers; an address setting unit (21) provided in the second microcomputer for composing an address value supplied by the first microcomputer and a value set in the offset register to feed address data to the third memory.

Multiprocessor system having offset address setting

A NAK register, for storing negative acknowledgment data in the case where a transmission has not been received normally, is newly installed as an RSP register other than a ACK register. By controlling the delivery of reception response (RSP) from these registers according to a multi-destination communication signal and an error detection signal at an RSP control circuit, it becomes possible to announce occurrence of a reception error and an overrun error at the reception side terminal to transmission side terminals and the other reception side terminals. Thereby, there exists reception response from reception side terminals, in a communication frame at multi-destination communication, and a multiplex communication apparatus can be obtained, which can detect whether or not all of a plurality of reception side terminal have received a transmission normally.

Multiplex communication control apparatus

A Data transmission device controlled by a processor which has a transmission control apparatus (14) which re-transmits transmission data which was previously set by a microcomputer (10) and which was unable to be transmitted in a first transmission attempt. The transmission control apparatus (14) has a transmit data word number comparing circuit (28) which determines whether a value of a set transmit data word number is within the limits prescribed by a communication standard. In the event of a failed transmission attempt, the microcomputer sets a transmit data word number greater than the number prescribed by the communication standard.

Data transmission system wherein the setting of the transmit data word

The microcomputer of the invention comprises a flip-flop which repeats setting and resetting of a monitor signal. The monitor signal is delivered from an external device in response to a PWM output signal for driving the external device. The flip-flop sets and resets at the front edge, of the monitor signal. The invention detects a failure of the external device according to the presence or absence of inversion of its held value. Hence, the failure of the external device operating at high speeds can be reliably detected by the microcomputer of the invention.

Apparatus and method for detecting failure of an external device by a

Data processing system including memory device having even-numbered addresses and odd-numbered addresses in which both an even-numbered address and an odd-numbered address are accessed in the long data bit length mode and either an even-numbered address or an odd-numbered address is accessed in the short data bit length mode, comprising a switching circuit 200 for carrying out the data communication with an odd-numbered address through a high-order data bus 6 or a low-order data bus 5 in the short data bit length mode, and a switching circuit 150 for carrying out the data communication with an odd-numbered address through the low-order data bus 5 in both the long and short data bit length modes. By virtue of this structure, the data communication through the low-order data bus only is made possible for both an even-numbered address and an odd-numbered address in the short data bit length mode.

Method of and system for processing data having bit length variable with

A pulse generator circuit includes an adder, a count register which holds the result of addition provided by the adder in order for the addition-result for recursive addition in the adder, a constant register holding a constant required for making said adder continue to perform count-up/count-down operation until a carry/borrow occurs, a parameter register for applying to said adder a correction value for changing, during a normal count-up/count-down operation, the time when carry/borrow occurs, a selector for selecting one of said constant and parameter registers for applying the value held in the selected register to said adder, and a shift register responsive to a carry/borrow occuring in the addition-result from said adder for shifting the content thereof.

Pulse generator circuit employing arithmetic function counter

A multifunctional memory comprises a mask ROM (2). When an 'L' level signal is applied to a control pin (EXT), data is read out from the ROM (2) in response to an address signal inputted from a multiplex pin (AD/DA). Thereafter, the data read out from the ROM (2) is outputted from the multiplex pin (AD/DA). In this case, an 'H' level signal is outputted from a chip select pin (CS). When an 'H' level signal is applied to the control pin (EXT), an 'L' level signal is outputted from the chip select pin (CE). Consequently, the EPROM (30) is rendered active. In addition, the address signal inputted from the multiplex pin (AD/DA) is outputted from a port/address pin (PORT/AD). Data is read out from the EPROM (30) in response to the address signal.

Semiconductor integrated circuit device comprising non-reprogrammable

A counter control method according to the present invention comprising the steps of:

Counter control method

A pulse generating circuit which, when a counting value of a counter and a value previously set at a register are coincident with each other, converts an output into the preset level to thereby generate each elementary pulse, and is provided with a register buffer for storing therein a value for defining the time, when the level of the pulse output is reconverted so that when the level of the pulse signal is converted, the stored value of the register buffer is set in the register through no software to thereby eliminate the influence on software processing with respect to the elemental pulse width, and is provided with a counter buffer for storing therein a counting start value to be set at the counter in addition to the above-mentioned construction so that the value is constructed to be desirably changeable to thereby enable the counting start value of the counter to be changeable each time the overflow occurs, thus enabling the cycle duration of the pulse signal to be changed with ease.

Pulse generating circuit

A disk driving mechanism is provided with a program memory section storing programs corresponding to a plurality of operational modes of the device and a mode set switch for applying an operational mode to an input/output section of the device. A central processing unit is provided for recognizing the operational mode set by said mode set switch, and for operating the device according to a program read out of the program memory corresponding to the selected operational mode. According to the invention, a floppy or hard disk drive may be operated by itself, without the aid of a host computer, for the purpose of self-diagnosis.

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Itami, Japan

Kikuo Muramatsu