Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Sandisk Corporation

Kikuko Sugimae

Masayuki Ichige

Hiroyuki Kutsukake

Riichiro Shirota

Takeshi Kamigaichi

Atsuhiro Sato

Fumitaka Arai

Yuji Takeuchi

Reika Ichihara

Yasuhiko Matsunaga

Yusuke Arayashiki

Koji Hashimoto

Satoshi Tanaka

Michiharu Matsui

Yoshihisa Iwata

Takayuki Miyazaki

Hiroaki Hazama

Makoto Sakuma

Noboru Shibata

Mitsuhiro Noguchi

Takuya Futatsuyama

Katsuya Nishiyama

Takuya Konno

Akiyuki Murayama

Motohiko Fujimatsu

Koji Sakui

Masaaki Higashitani

Tetsuya Hayashi

Koji Kato

Tuan Duc Pham

Masumi Saitoh

Yusuke Kobayashi

Akihiro Kajita

Junya Matsunami

Chika Tanaka

Tatsuo Izumi

Masato Endo

Keisuke Yonehama

Yoshiko Kato

Kiyohito Nishihara

Kenji Gomikawa

Yasushi Kameda

Hidefumi Nawata

Takamichi Tsuchiya

Kyosuke Sano

Kanae Uchida

According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2second distributions are separately formed two by two. The circuit then sets 2third distributions for the 2sections.

Semiconductor memory device and method

A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

Resistive random access memory device with three-dimensional cross-point structure and method of operating the same

A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.

Semiconductor memory device

A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

High-voltage transistor having shielding gate

A resistance random access memory device includes a control circuit. The control circuit applies a first voltage between the plurality of second interconnects and one of the first interconnects for a first time when switching resistance states of the variable resistance members from a first state to a second state, and the control circuit applies a second voltage between the plurality of second interconnects and the one of the first interconnects for a second time after applying the first voltage when the resistance state of one or more of the variable resistance members of a plurality of the variable resistance members connected to the one of the first interconnects is in the first state. The second voltage has the same polarity as the first voltage and is lower than the first voltage. The second time is longer than the first time.

Resistance random access memory device and method for operating same

A semiconductor storage device includes a variable resistive element, which changes a resistance value according to a polarity and a magnitude of an applied voltage, as a memory element. The semiconductor storage device includes a standby mode in which a power source voltage or a ground voltage is applied to both of a word line and a bit line. The semiconductor storage device includes a data write mode in which a voltage difference equal to or more than a first voltage is applied between the word line and the bit line. The semiconductor storage device includes a read mode in which a voltage difference smaller than the first voltage is applied between the word line and the bit line by changing only one voltage of the word line and the bit line which is applied in the standby mode, and data written in the memory element is read.

Semiconductor storage device and driving method of the same

A resistance variable memory has a controller configured to control a voltage to be applied to the memory cell. The controller has a reset operation to bring the memory cell into a reset state, a first operation to apply a set voltage between the first wire and the second wire, a second operation to determine whether a current flowing to the memory cell to be set exceeds a first threshold when a first reading voltage is applied between the first wire and the second wire, a third operation to determine whether a current flowing to the memory cell to be set exceeds a second threshold when a second reading voltage is applied between the first wire and the second wire, and a fourth operation to apply a second reset voltage, between the first wire and the second wire.

Variable resistance memory device and verify method thereof

According to one embodiment, a memory device includes a substrate, a conductive wire provided above the substrate to extend in a first direction and including an end portion decreases in width toward a distal end, and a contact connected to the conductive wire at least a side surface of the end portion. The end portion includes, in the contact, a first portion having a shortest distance from an outer peripheral surface of the contact and a second portion extending from the first portion and having a distance from the outer peripheral surface of the contact longer than the shortest distance.

Memory device and manufacturing method therefor

A non-volatile semiconductor memory device includes a cell array layer including a first wire, a memory cell, and a second wire, and a control circuit. When performing set operation for setting the memory cell to a low resistance state, until a resistance value of the memory cell becomes lower than a predetermined resistance value, the control circuit repeating: applying a first voltage for setting to the memory cell; and a verify read verifying that the resistance value of the memory cell has become lower than the predetermined resistance value. After the verify read, the control circuit applies a second voltage having a different polarity from the first voltage to the memory cell before applying the first voltage that follows.

Non-volatile semiconductor memory device

According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value.

Semiconductor storage device

Growing community of inventors

Yokohama, Japan

Kikuko Sugimae