Samsung Electronics Co., Ltd.

Pohang University of Science and Technology Foundation

Lg Electronics Inc.

Kijun Lee

Myungkyu Lee

Sunghye Cho

Sungrae Kim

Yeonggeol Song

Junjin Kong

Eunae Lee

Sanguhn Cha

Kyomin Sohn

Chanki Kim

Jaehong Kim

Dong-Min Shin

Seongmuk Kang

Sejin Lim

Hong Rak Son

Yesin Ryu

Hoyoun Kim

Daehyun Kim

Jaeyoun Youn

Kyeongcheol Yang

Isak Hwang

Yong June Kim

Hong-Rak Son

Heeseok Eun

Jiho Kim

Kiheung Kim

Hyeran Kim

Bohwan Jun

Jinhoon Jang

Chisung Oh

Sung-Rae Kim

Seung-Chan Lim

Changyong Lee

Jungsoo Chung

Suhun Lim

Jongmin Lee

Eun Chu Oh

Youngmin Kang

Kyung-ho Lee

Minuk Kim

Sukhan Lee

Junhyung Kim

Younggeon Yoo

Geunyeong Yu

Youngcheon Kwon

Namsung Kim

Youngjun Hwang

Beom Kyu Shin

Yong-June Kim

Jin-Hoon Jang

Hyongryol Hwang

Ki-Heung Kim

JunHyung Kim

Sunggi Ahn

Eun Ae Lee

Byeonggyu Park

Seokha Hwang

Eunchul Kwon

Ikjoon Chang

An example CXL (Compute eXpress Link)-based memory module includes a memory device and a controller. The memory device includes a plurality of volatile memory cells and stores data or reads the stored data. The controller communicates with a host device through a CXL interface and controls the memory device. The controller includes an error correction code (ECC) circuit that generates a first codeword by adding a parity vector generated based on Reed-Solomon encoding to data received from the host device, an error injecting circuit that generates an error symbol and generates a second codeword by injecting the error symbol into at least a portion of the first codeword, and a memory device interface that controls the memory device such that the second codeword where the error symbol is injected is stored in the memory device. The controller determines a number of error symbols to be injected into the second codeword.

Semiconductor memory device and operating method thereof

A memory device includes an ECC circuit that performs error correction code (ECC) encoding on input data to generate write data, and a memory cell array including a plurality of memory cells that stores the write data. The ECC circuit includes a data splitter that splits the input data into first sub-data and second sub-data, a first ECC encoder that performs ECC encoding on the first sub-data to generate first sub-parity data, a second ECC encoder that performs ECC encoding on the second sub-data to generate second sub-parity data, and a data scrambler that performs a data scrambling operation with respect to the first sub-data, the second sub-data, the first sub-parity data, and the second sub-parity data based on a structure of the memory cell array to generate the write data.

Memory device and operation method thereof

A memory system includes a plurality of volatile memory devices and a memory controller. The memory controller causes different amounts of error correction parity information to be generated depending on a request from a host device and depending on failed memory cell counts. The memory controller includes an error correction level (ECL) manager configured to receive cache line data from the host device through the host interface, and output an error correction code (ECC) control signal indicating one of a first correction level and a second correction level. The correction levels are based on cell reliability information and data reliability request information. The data reliability request information is associated with the cache line data. An ECC engine generates first parity symbols associated with the cache line data, and may, depending on the ECC control signal, generate additional parity symbols.

Memory system, method of operating the same, and electronic system including the same

A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

Semiconductor memory device including a cyclic redundancy check engine and memory system including the same

A memory device includes a memory cell array and an error correction code (ECC) circuit. The ECC circuit, which is configured to correct an error in a data code read out from the memory cell array, includes: (i) a syndrome calculating unit configured to operate a plurality of syndromes based on the data code and an H-matrix, (ii) an error location detecting unit configured to generate an error vector based on the plurality of syndromes, and (iii) an error correcting unit configured to correct an error within the data code based on the error vector, and output corrected data.

Error correction code circuit, memory device including error correction code circuit, and operation method of error correction code

A memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer managing circuit, which is configured to detect a row hammer address based on a pre row hammer address, and each of a plurality of input row addresses associated with a plurality of accesses during a monitoring period for monitoring the plurality of accesses to a plurality of the rows of memory cells. A refresh control circuit is provided and is configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address.

Memory devices and methods thereof for managing row hammer events therein

A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

Integrated circuit memory devices having efficient row hammer management and memory systems including the same

A memory controller to control a memory module including a plurality of data chips, a first parity chip and a second parity chip, includes a system error correction code (ECC) engine and a processor to control the system ECC engine. The system ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder selects one of a plurality of ECC decoding schemes based on decoding status flags and corrects a plurality of symbol errors in a read codeword set from the memory module by performing an ECC decoding on the read codeword set based on the selected decoding scheme and the parity check matrix. The decoding status flags are provided from the plurality of data chips and each of the decoding status flags indicates whether at least one error bit is detected in respective one of the plurality of data chips.

Memory controllers and memory systems including the same

A storage circuit includes a multi-stage latch circuit having first to fourth transistor pairs therein, which respectively include a pull-up transistor and a pull-down transistor connected in series through a corresponding one of first to fourth storage nodes. An access circuit is provided, which has a plurality of access transistors of different conductivity type therein. The access transistors are electrically coupled to at least two of the first to fourth storage nodes and configured to enable writing of data bits into at least some of the first to fourth storage nodes, and reading of data bits from at least some of the first to fourth storage nodes. A control circuit is provided, which controls the access circuit during the writing and reading.

Latch-based storage circuits having efficient integrated circuit layouts

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

Semiconductor memory device and method of operating the same

A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.

Memory device and refresh method thereof

A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.

Memory device performing refresh operation and method of operating the same

An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.

Error correction circuit, memory system, and error correction method

Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.

Error correction code circuit, memory device including error correction code circuit, and operation method of error correction code circuit

A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

Semiconductor memory devices

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Seoul, South Korea

Kijun Lee