Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Kiichiro Tamaru

Akira Kanuma

Koichi Tanaka

Yasuo Yamada

Toshiyuki Yaguchi

Yoko Ookita

A microprocessor device has an operand address register for storing an operand access address for an operand access, an access generation instruction address register for storing an access generation instruction address having caused the operand access and an operand data register for storing input/output data for the address indicated by the operand address. A multiplexer, whose operation is controlled by a selection signal provided from outside of the microprocessor, outputs the operand address or the access generation instruction address to an address pin of the microprocessor. An emulator device includes the above microprocessor device and a hold circuit, connected to the address pin in the microprocessor, for holding the data output from the microprocessor through the address pin. An address signal line is connected to the hold circuit. A trace memory stores the information transferred through the address pin as trace information during a real-time trace operation. A trace control circuit generates the selection signal and the hold signal to the hold circuit and generates a store signal. The hold circuit outputs the operand address to the address signal line when the hold signal and the selection signal are in the enable state.

Microprocessor device and emulator device thereof

In a data processing apparatus, when making an access to a specific object to be accessed, the data processor supplies an access control signal to a plurality of control signal generators. The data processor further supplies accessed object type data to the accessed object type determining circuit. The determining circuit determines the type of the accessed object on the basis of the accessed object type data, and selectively drives the control signal generator corresponding to the accessed object. The control signal generator driven converts the access control signal into a control signal adapted for the accessed object. An address signal and data are transferred between the specific accessed object supplied with this control signal and the data processor via the address bus and data bus.

Apparatus for selectively accessing different memory types by storing

In an address multiplexing apparatus for multiplexing address data to be supplied to 64K bit, 256K bit, and 1M bit DRAMs, upon multiplexing of address data, input address data of 20 bits are classified into two groups, i.e., the lower 16 bits and the upper 4 bits. The lower 16-bit group is multiplexed so that the upper 8 bits serve as row address data, and the remaining lower 8 bits serve as column address data. In the upper 4-bit group, adjacent bits are multiplexed. The apparatus can be commonly used for the three memories having different capacities with the simple circuit arrangement, and page mode access can be executed.

Address multiplexing apparatus

A logic circuit has two pairs of input terminals to each of which is applied a pair of input signals opposite in phase and a pair of output terminals for deriving a pair of output signals corresponding to the logical states of the two pairs of input signals. The logic circuit is further provided with a holding circuit which is adapted to hold the output signals in the same logical state when a pair of input signal having the same phase are applied to the input terminals.

Logic circuit having an error detection function

In a system including LSIs, the signature register used for self-testing the LSI functions is assigned to one register accessible by a machine instruction. The signature is calculated in the self-test operation, and the calculation result is updated depending on the result from the execution of the machine instruction. With the above technical idea, the test function for the LSI function is available not only for the test mode, but also for the normal operation. This simplifies the self-test program for testing the functions of the application system.

Semiconductor integrated circuit device

The logic circuit is disclosed. Even if the system is stopped while an output latch circuit is in the latching state, when an input latch circuit is latching an input signal, the logic gate remains in the precharge mode, whereas the precharge signal as generated by a precharge signal generator circuit is in the 'H' level, i.e. a precharge level. Therefore, the logic output from the logic gate is never erased. Within a period that the input and output latch circuits are both in the latching state, the system can be stopped without erasing the logic output.

Stop/restart latch

A communication control apparatus wherein the version number of a communication control program in a packet accepted by a receive circuit is compared at a comparator with that of the local station. When the version for the local station is determined to be older than the version for the remote station, the apparatus receives the latest communication control program from the remote station and stores it in a rewritable memory, thereby allowing communication using the latest version.

Communication control apparatus

A multi-level priority interrupt system is used for controlling the access of input/output control devices to a host computer which is connected to the devices and controls their operation. The input/output control devices each of which is contained on a different LSI chip, output different levels of interrupt requests to the host computer. During operation, each input/output control device outputs an interrupt signal of a frequency determined by a level of an interrupt to be sent to the host computer. The interrupt signal is supplied from one external terminal of the input/output control device. Upon receipt of the interrupt signals, the host computer determines a priority of the interrupt from the frequency of the signal and then executes a corresponding interrupt routine.

Frequency-coded multi-level interrupt control system for a

A digital information transfer apparatus includes N shift registers (1 through N) for storing digital information supplied to and from N respective function modules, and a common bus connected to the shift registers for parallel transfer of digital information. The shift registers are serially connected by a scan path to form a large scale shift register. An error detector in the transferring control circuit detects a failure on the common bus, and supplies a serial output signal of the Nth shift register to the 1st shift register. The processing circuit of the 1st function module rotates the contents of the 1st to Nth shift registers, through the scan path.

Fault-compensating digital information transfer apparatus

In floating-point multiplication, the sum of the exponents of the two operands is determined by the use of a single adder. The exponents are modified either before they are inputted to the adder or at the output of the adder. A carry signal of '1' is applied whenever addition is carried out. A signal indicative of occurrence of underflow or overflow is also obtained.

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Tokyo, Japan

Kiichiro Tamaru