Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Fujitsu Vlsi Limited

Kiichiro Iga

Tomohiro Fukuoka

Kenji Yamada

Masaru Sawada

Yuji Watarai

Takeshi Seki

Chihiro Sekiya

An image processing system is disclosed that includes a buffer unit configured to store a predetermined pixel and peripheral pixels neighboring the predetermined pixel in image data in a first direction and a second direction perpendicular to the first direction; and a first edge-detecting circuit configured to calculate a maximum value and a minimum value of a set of pixels selected from the peripheral pixels that have the same color as the predetermined pixel to calculate a difference value between the maximum value and the minimum value.

Image processing system that removes noise contained in image data

An encoded data transfer device () includes a JPEG compressing section () that converts image data to encoded data, a data buffer () that stores the encoded data from the JPEG compressing section (), a stored data amount detecting section () that detects the stored data amount of the encoded data stored in the data buffer () reaching a predetermined amount DC, a data transfer section () that transfers the encoded data stored in the data buffer () to the outside in response to a result of the stored data amount detecting section (), and a transfer data amount detecting section () that detects the predetermined amount DC of the encoded data being transferred from the data transferring section (). In the data buffer (), transfer from the JPEG compressing section () is inhibited in response to a result of the stored data amount detecting section (), and transfer from the JPEG compressing section () is started in response to a transfer data amount detecting section ().

Encoded data transfer device and encoded data transferring method

An image processor for lowering data transfer speed. A JPEG compression circuit performs two-dimensional compression process on data output from a YCbCr conversion circuit to generate compressed image data. A timing signal generator changes the frequency of a transfer clock signal in accordance with the compressed image data. An output circuit outputs the compressed image data in accordance with the transfer clock signal.

Image processor, imaging device, and image processing system use with image memory

A format conversion circuit converts RGB data to YCbCr data. A one-dimensional compression circuit performs one-dimensional compression process on the YCbCr data to generate one-dimension compression image data and provides the one-dimension compression image data to a base band LSI. The one-dimensional compression circuit includes a memory area that is relatively small but sufficient for holding several bytes of data subject to the compression process.

Image processor of imaging apparatus

A circuit for correcting distortion produced by the lens of a digital camera when generating an image, which includes pixels. The correction circuit includes an address generation circuit for generating horizontal and vertical addresses for each pixel. A coefficient storage circuit stores a pitch correction coefficient associated with the horizontal or vertical address of each pixel. A storage circuit stores data for an image for which distortion is uncorrected in association with an address of the uncorrected image. A calculation circuit calculates the address of data of the uncorrected image corresponding to each pixel using the associated horizontal and vertical addresses and pitch correction coefficient of the horizontal or vertical address. A processing circuit reads the data of the uncorrected image from the storage circuit and generates data for a distortion-corrected image.

Distortion correction circuit for generating distortion-corrected image using data for uncorrected image

The invention provides an image processing circuit having a capability of performing a reduction (resizing) process and an enlargement process on horizontal-scanning-line data inputted in synchronization with an input horizontal synchronization signal, and subsequently adjusting the horizontal synchronization signals so that the input horizontal-scanning-line data is made transferable to external devices in real time, and an image processing method therefor. A reducing unit thins out n-lines of the input horizontal synchronization signals out of m-lines of the input horizontal synchronization signals HD. When an enlarging unit enlarges the image data by an enlargement ratio k (k: natural number) in the vertical direction, the enlarging unit inserts (k&#x2212;1) lines of the second horizontal synchronization signals for data transmission EHSYNCin the transmitting horizontal-synchronization-signal interval time TCbetween adjacent first horizontal synchronization signals for data. transmission EHSYNCwith predetermined intervals. A composing unit merges the first horizontal synchronization signals for data transmission EHSYNCand the second horizontal synchronization signals for data transmission EHSYNCto give horizontal synchronization signals for data transmission EHSYNC.

Circuit to resize and enlarge an image signal and resizing and enlargement method for an image signal

A microcomputer includes a processor and an emulator interface circuit that provides processor state information to an external emulator. The emulator interface circuit operates at a clock speed that is lower than the clock speed of the processor and provides the state information at predetermined intervals, such as after a predetermined number of processor clock pulses. The state information may also be provided after a specified number of instruction fetches have occurred.

Microcomputer with emulator interface

A product-sum operation unit including a multiplying unit, a pipeline register for loading a multiplication result, an adder unit for adding a summand and either an output of the pipeline register or an addend. A timing signal generating unit generates first and second timing signals (T1, T2) that are synchronized with first and second clocks (CK1, CK2). A first instruction latch loads an instruction synchronously with the first timing signal (T1) to output a first control signal. A second instruction latch loads an instruction loaded in the first instruction latch synchronously with the second timing signal (T2) to output the second control signal. A control signal selector outputs the second control signal in response to the first timing signal (T1), and also outputs the first control signal to the adder unit, in response to the second timing signal (T2).

Growing community of inventors

Kasugai, Japan

Kiichiro Iga