Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Synaptics Japan Gk

Other

Synaptics Display Devices Gk

Synpatics Display Devices Gk

Kiichi Makuta

Shinya Suzuki

Toshihiro Tanaka

Yutaka Shinagawa

Yoshiki Kawajiri

Masamichi Fujito

Takashi Yamaki

Masashi Wada

Kazufumi Suzukawa

Hideo Kasai

Akihiro Fujita

Masashii Wada

Atsushi Toukairin

Yoshinori Ura

Keita Tsubakino

Toshikazu Arai

Jun Uchida

Iori Shiraishi

Satoshi Saito

Masaru Iizuka

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.

Semiconductor device

A display drive circuit includes: source amplifiers capable of driving source lines of a display panel connected thereto; preamplifiers capable of outputting first gradation voltages; source circuits each including a division of the source amplifiers, provided that the source amplifiers are divided equally; and resistance arrays. Each source circuit is provided with one of the resistance arrays. Each resistance array divides input first gradation voltages to generate second gradation voltages and provides them to the corresponding source circuit. The worsening of the capability of converging of gradation lines for supplying second gradation voltages to the source circuits can be suppressed without providing gradation-voltage-generation circuits even with a display driver IC having an increased long side length, or more than one display driver IC provided.

Display drive circuit and display device

A gradation voltage corresponding to a display data is input to a signal electrode driving circuit. The signal electrode driving circuit includes a voltage output circuit which outputs a drive voltage corresponding to the input gradation voltage, and a slew rate assist circuit which accelerates a transition of an output voltage of the voltage output circuit. The slew rate assist circuit accelerates the transition of the output voltage after a predetermined time from a start of transition of the gradation voltage.

Display driver

A semiconductor device includes a main structure, active bumps and dummy bumps which are provided over a surface of the main structure. The active bumps are arranged in first to n-th rows. The active bumps positioned in each row are arrayed in a first direction with a predetermined first pitch. The first to n-th rows of the active bumps are arrayed in a second direction perpendicular to the first direction. For j being any integer from one to n&#x2212;1, a (j+1)-th row are shifted in the second direction from a j-th row of the active bumps by a second pitch and shifted in the first direction from the j-th row of the active bumps by a predetermined sub-pitch. The dummy bumps are arrayed in the first direction with the first pitch, and the length of each of the dummy bumps in the second direction is longer than the second pitch.

Semiconductor device with external connection bumps

Provided is a display control device capable of coping with high-resolution display readily in terms of conducting data write and read on a frame buffer memory in time for the timing of display. The display control device has a plurality of line buffers, and is arranged so that a writing process for writing, into part of the line buffers, display lines of display data from outside, and a reading process for reading out written display lines of display data from other line buffers can be conducted in parallel. In the display control device, display-line data read out from the line buffers are compressed and stored in the frame buffer memory. The compression-display data read out from the frame buffer memory are read out for each line, and decompressed into display lines of display data. The decompressed display data are used to drive signal electrodes of a display device.

Display control device and data processing system

Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic '1' (or logic '0'), writing operation to bits corresponding to write data having the logic &#x201c;0&#x201d; (or logic &#x201c;1) is successively performed.

Nonvolatile memory, semiconductor device, and method of programming to nonvolatile memory

A nonvolatile semiconductor memory device includes a memory array which comprises a plurality of memory cells of a type wherein predetermined voltages are applied to selected memory cells to change their threshold voltages, whereby information are stored therein according to the difference between the threshold voltages, and whose some memory cells are used as spare memory cells. The nonvolatile semiconductor memory device is provided with a latch circuit connected to each bit line of the memory array through a transmission switch. The memory array is capable of storing therein at least substitutional information for replacing a defective bit by the spare memory cell. The substitutional information is transferred from the memory array to the latch circuit through the transmission switch and held in the latch circuit.

Nonvolatile semiconductor memory device

Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic &ldquo;1&rdquo; (or logic &ldquo;0&rdquo;), writing operation to bits corresponding to write data having the logic &ldquo;0&rdquo; (or logic &ldquo;1) is successively performed.

Nonvolatile memory, semiconductor device and method of programming to nonvolatile memory

Growing community of inventors

Tokyo, Japan

Kiichi Makuta