Samsung Electronics Co., Ltd.

Kihyun Hwang

Juyul Lee

Myoungbum Lee

Kwangmin Park

Yong-Hoon Son

Hanmei Choi

Dongwoo Kim

JinGyun Kim

Dongchul Yoo

Woonkyung Lee

Jaeyoung Ahn

Chanjin Park

Sunghae Lee

Seungjae Baik

Jung Ho Kim

Daehyun Jang

Toshiro Nakanishi

Sunghoi Hur

Kwang Soo Seol

Sunggil Kim

Junkyu Yang

Jintae Noh

Sangryol Yang

Ju-Eun Kim

Wansik Hwang

Jinbum Kim

Kyungin Choi

Phil Ouk Nam

Siyoung Choi

Bio Kim

SeungHyun Lim

Haejun Yu

Juwan Lim

Jongsik Chun

Byoungsun Ju

Seung Hun Lee

Keun Hwi Cho

Jung-Hwan Lee

Dahye Kim

Seokhoon Kim

Sangmoon Lee

Bonyoung Koo

Jin-Kyu Kang

Jaemun Kim

Ilgyou Shin

Jeeyong Kim

Gukhyon Yon

Chaeho Kim

Hansoo Kim

Sunil Shim

Jaehoon Jang

Wonseok Cho

Sanghoon Ahn

Jae-young Ahn

Kyunghyun Kim

Jeonghee Park

Jaegoo Lee

Daehong Eom

Oik Kwon

Se-Ho Cha

Dongkyum Kim

Jun-Youl Yang

Sungkweon Baek

Chadong Yeo

Gyungjin Min

Hanvit Yang

Seongsoo Lee

Juhyung Kim

Wookhyoung Lee

Yoochul Kong

Bumsu Kim

Jung-ho Kim

Seunghun Lee

Gyeom Kim

Sunjung Kim

Dohee Kim

Soodoo Chae

Hyun Kyu Park

Jin Ha Jeong

Woojin Jang

Byong-Hyun Jang

Junggeun Jee

Seungmok Shin

Su-Jin Shin

Hyun Ku Park

Hunhyeong Lim

ZongLiang Huo

Youngseon Son

Byong-hyun Jang

Kwangyoung Lee

Yong-Hoon Sang

A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

Semiconductor device having a liner layer and method of fabricating the same

Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

Semiconductor memory device having insulation patterns and cell gate patterns

An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region.

Integrated circuit device

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Three-dimensional semiconductor memory devices and methods of fabricating the same

A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.

Variable resistance memory device having an anti-oxidation layer and a method of manufacturing the same

Semiconductor device including a field effect transistor and method of fabricating the same

A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section. A vertical stack of a plurality of gate lines can each extend horizontally around the filling insulating pattern and the plurality of active channel patterns.

Nonvolatile semiconductor devices including non-circular shaped channel patterns and methods of manufacturing the same

The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

Semiconductor memory devices and methods for fabricating the same

A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

Three-dimensional semiconductor memory device and method of fabricating the same

A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

Semiconductor memory devices and methods of fabricating the same

Growing community of inventors

Seongnam-si, South Korea

Kihyun Hwang