Samsung Electronics Co., Ltd.

Kiho Yang

Seunghune Yang

Sibo Cai

Kaiyuan Chi

Disclosed is a semiconductor device comprising a substrate, a first dielectric layer and a second dielectric layer that are sequentially stacked on the substrate, a contact that penetrates the first dielectric layer and extends toward the substrate, and a conductive line that is provided in the second dielectric layer and electrically connected to the contact, The conductive line extends in a first direction. The contact comprises a lower segment in the first dielectric layer and an upper segment in the second dielectric layer. A width in a second direction of the conductive line decreases with decreasing distance from the substrate. The second direction intersects the first direction. A sidewall of the upper segment of the contact is in contact with the conductive line.

Semiconductor devices including contacts and conductive line interfaces with contacting sidewalls

The inventive concepts provide a method for inspecting a pattern, a method for manufacturing a semiconductor device, and an apparatus used according to the methods. The method for inspecting a pattern includes detecting a measured image corresponding to a pattern formed on a substrate, detecting a first hot spot corresponding to a ghost image of the measured image, with the first hot spot representing a defect of the pattern, and detecting a second hot spot that has an area that is wider than that of the first hot spot.

Method for inspecting pattern and an apparatus for manufacturing a semiconductor device using the same

A pattern analysis method of a semiconductor device includes extracting a contour image of material layer patterns formed on a wafer, calculating an individual density value (DV) representing an area difference between the contour image and a target layout image, scoring the material layer patterns on the wafer using the individual DV, identifying a failure pattern among the scored material layer patterns, calculating coordinates of the identified failure pattern and displaying the coordinates on a critical dimension-scanning electron microscopy (CD-SEM) image, inputting a reference DV in the computer and automatically sorting the material layer patterns into material layer patterns having a hotspot and material layer patterns not having a hotspot, and reviewing the sorted material layer patterns having the hotspot.

Pattern analysis method of a semiconductor device

Inventive concepts provide a method of inspecting a semiconductor device including obtaining inspection image data of an inspection pattern of an inspection layer on a substrate. The method may include extracting inspection contour data including an inspection pattern contour from the inspection image data, and merging the inspection contour data with comparison contour data of a comparison layer to obtain merged data. The comparison layer may overlap the inspection layer. The method may also include determining a horizontal distance between the inspection pattern contour and a comparison pattern contour of the comparison contour data based on the merged data.

Growing community of inventors

Hwaseong-si, South Korea

Kiho Yang