Vlsi Technology, Inc.

Kieu-Huong Do

Sunil V Ashtaputre

Mark R Hartoog

Charles H Ng

Prasad Sakhamuri

In a method for providing routing between logic cells, the logic cells are arranged in rows. Intercell connectors within each row of logic cells are aligned, for example in the middle of the rows, to form channel boundaries. The intercell connectors are then channel routed in metal layers above the logic cells. Alternately, intercell connectors are placed within the logic cells, however, these intercell connectors are not necessarily aligned. For each intercell connector which is not on a boundary of a routing channel, a substitute connector is located at the boundary of a routing channel. The substitute connectors and the intercell connectors which are on the boundaries of the routing channels are channel routed. Length of routing segments are then adjusted to substitute connectors to extend to intercell connectors instead of the substitute connectors.

Method of routing three layer metal gate arrays using a channel router

A method of routing interconnections of devices in a planar field by the use of a computer. The method effectively shortens the length of all interconnections, including interconnections which connect points on the same device, in accordance with design rules. Also, the layers constituting the planar field can be assigned weights to effectively minimize the appearance of interconnections in the layer having the highest assigned weight.

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San Jose, CA, United States of America

Kieu-Huong Do