Analog Devices,inc.

Kieran K Heffernan

David J Clarke

Michael P Daly

Javier Alejandro Salcedo

Gavin Patrick Cosgrave

Stephen Denis Heffernan

John Twomey

Juan Luo

Brian B Moane

Seamus Murnane

Denis Ellis

Shaun Bradley

Michael G Tuthill

Brian Anthony Moane

Tomas Tansley

Denis J Doyle

John Patrick Purcell

Liam Joseph White

Vincent James Troy

Christian Willibald B&ouml;hm

Keith A Moloney

Yang Ling

Christian Willibald Böhm

Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Junction-isolated blocking voltage structures with integrated protection structures

Junction-isolated blocking voltage devices with integrated protection structures and methods of forming the same

A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares the frequency of the reference oscillator clock with the frequency of a calibratable oscillator clock, turns off the reference oscillator clock and adjusts, in response to a difference in those frequencies, the frequency of the calibratable oscillator clock towards that of the reference oscillator clock.

Microprocessor programmable clock calibration system and method

A synchronization pulse detector includes an absolute value independent shape detector for processing samples of an input signal having a synchronization pulse and a plurality of non-synchronization pulses to determine whether such samples have a predetermined sequence. The predetermined sequence includes a first and second absolute value independent time-varying portions and a first and second absolute value independent non-time varying portions. One of the first and second absolute value independent time-varying portions having a positive slope and the other one of the first and second absolute value independent time-varying portions having a negative slope.

Synchronization pulse detection circuit

A detector circuit ( ) for detecting the presence or absence of a television ( ) on an output ( ) of a video DAC ( ) comprises a comparator ( ) for comparing a voltage developed by the video signal on a control resistor R with a reference voltage of 0.5 volts. The resistor R is of 75 ohms and matches the internal impedance R of 75 ohms of the television ( ). A latch ( ) latches the output from the comparator ( ) onto an output pin Q when the voltage developed across the control resistor R is developed by an equalisation pulse of the vertical blanking interval of the video signal. In the presence of a television ( ) the voltage developed across the control resistor R is 0.35 volts, which pulls the output of the comparator ( ) low, while in the absence of a television ( ) the voltage developed across the control resistor R is 0.7 volts which pulls the output of the comparator ( ) high. A control logic control circuit ( ) reads the output pin Q of the latch ( ) for powering up or powering down the video DAC ( ) as appropriate.

Method and a circuit for detecting the presence of a television or other device on the output of a video digital to analog converter

A synchronization pulse detector for detecting a synchronization pulse within an input signal. The input signal has &ldquo;level&rdquo; portions (i.e., substantially non-time varying portions) and &ldquo;transition&rdquo; portions (i.e., substantially time varying portions). The pulse detector includes a pulse shape detector for determining each time the input signal has a sequence of a first &ldquo;level&rdquo; portion, followed by a first &ldquo;transition&rdquo; portion, followed by a second &ldquo;level&rdquo; portion, followed by a second &ldquo;transition&rdquo; portion followed by a third &ldquo;level&rdquo; portion, one of the first and second &ldquo;transition&rdquo; portions being positive and the other one of the first and second &ldquo;transition&rdquo; portions being negative. Each time such sequence is determined a pulse_shape detected pulse is produced. An evaluator is provided to reject invalid pulse_shape detected pulses. In one embodiment, the input signal is a video signal and the evaluator includes a time window for determining whether such shape_detected pulses are produced at a predetermined rate expected for the series of synchronization pulses. The evaluator includes a voltage window responsive to the produced shape_detected pulses and their associated values of the second &ldquo;level&rdquo; portions for determining whether one of such produced second &ldquo;level&rdquo; portions is substantially the same as or lower but not higher than the lowest DC value recorded during the time-equivalent of one line of video. The evaluator may include both the time window and the voltage window. The voltage window is mainly used to acquire an initial lock to an unknown and not yet clamped video signal.

An input protection device is provided for protecting a circuit structure which is coupled to a first node, the device comprising a first lightly-doped region of P-type material with a lightly doped well of N-type material formed in it. Two regions of heavily doped N-type and P-type material, which are electrically connected to the first node, are formed in the well of N-type material. A third heavily doped region of N type material is formed in the first lightly-doped region of P-type material and is electrically connected to a reference node. In a first aspect of this invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this first aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node. In a second aspect to the invention, a further region of heavily doped P-type material is formed in the first lightly-doped region of P-type material. In a third aspect to the invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this third aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node, with a further region of heavily doped P-type material formed in the first lightly-doped region of P-type material. Accordingly, an input protection device for protecting pins of an integrated circuit is described having both bipolar and unipolar characteristics. The input protection device may be constructed as a discrete device or as part of an integrated circuit and provides for breakdown voltages in excess of a supply voltage to an integrated circuit. The characteristics, in particular the breakdown voltage, of the input protection device are alterable by adjusting its layout, in contrast to a known method of altering such characteristics by altering doping levels.

SCR cell for electrical overstress protection of electronic circuits

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Patrickswell, Ireland

Kieran K Heffernan