Kandou Labs, S.a.

Kanou Labs Sa

Kiarash Gharibdoust

Armin Tajalli

Ali Hormati

Suhas Rattan

Milad Ataei Ashtiani

Pavan Kumar Jampani

Chen Cao

Abdelsalam Ahmed Hassanin

Pallavi Muktesh

Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element.

Low latency combined clock data recovery logic network and charge pump circuit

Dual mode T-switches driven by at least one low-impedance switch driver, to connect at least four wires of a multiwire bus to a multi-input comparator (MIC) of a plurality of MICs in a first mode of Orthogonal Vector Signaling operation, and in a full-duplex mode of operation, using the low-impedance switch driver to disable a corresponding subset of T-switches to selectively disconnect a pair of wires of the multiwire bus from the MIC while using low-impedance enable signal paths in the low-impedance switch drivers to shunt capacitively-coupled interfering outbound signals received at the MIC from the selectively disconnected pair of wires in the full-duplex mode of operation.

Low-impedance switch driver in passive multi-input comparator for isolation of transmit signals in multi-mode configuration

Methods and systems are described for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval, generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval, comparing the first and the second early-late vote measurements, and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote measurements are within a predetermined threshold.

Clock and data recovery lock detection circuit for verifying lock condition in presence of imbalanced early to late vote ratios

Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.

Dynamic integration time adjustment of a clocked data sampler using a static analog calibration circuit

The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.

Amplifier with adjustable high-frequency gain using varactor diodes

Methods and systems are described for generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.

Measurement and correction of multiphase clock duty cycle and skew

Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.

Passive multi-input comparator for orthogonal codes on a multi-wire bus

Methods and systems are described for selectively providing a signal path from a respective wire of a multi-wire bus to at least one corresponding data signal output node of at least one set of differential data signal output nodes using a respective switching element in a respective set of signal path circuits connected in parallel, and generating a set of discharge currents, each discharge current of the set of discharge currents generated through a respective resistive element in the respective set of signal path circuits to discharge a portion of a voltage pulse on the respective wire of the multi-wire bus to one or more metallic planes via a respective localized ESD protection circuit, the respective resistive element and the respective localized ESD protection circuit connected between the respective wire and the respective switching element.

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Lonay, Switzerland

Kiarash Gharibdoust