Globalfoundries Singapore Pte. Ltd.

Kian Ming Tan

Khee Yong Lim

Elgin Kiok Boone Quek

Jae Gon Lee

Chunshan Yin

Elgin Kiok Quek

Kiok Boone Elgin Quek

Guangyu Huang

Xinshu Cai

Fan Zhang

Zhiqiang Teo

Fangxin Deng

Structures for an avalanche photodetector and methods of forming a structure for an avalanche photodetector. The structure comprises a substrate having a first conductivity type, a first semiconductor layer that defines an absorption region of the avalanche photodetector, a dielectric layer between the first semiconductor layer and the substrate, a charge control region comprising a semiconductor material having a second conductivity type opposite to the first conductivity type and a different bandgap from the first semiconductor layer, and a second semiconductor layer that extends through the dielectric layer from the charge control region to the substrate. The second semiconductor layer defines a multiplication region of the avalanche photodetector.

Avalanche photodetectors with a combined lateral and vertical arrangement

According to various embodiments, a memory cell may include a substrate of a first conductivity type, the substrate having first and second regions of a second conductivity type spaced apart and defining a channel region therebetween. The memory cell may further include a word line arranged over a portion of the channel region nearer to the first region, an erase gate arranged over the second region, a floating gate arranged over another portion of the channel region nearer to the second region and between the word line and the erase gate, and a coupling gate arranged over a top end of the floating gate. The floating gate includes the top end, a bottom end, a first side extending from the top end to the bottom end and facing the erase gate, and a second side extending from the top end to the bottom end and facing the word line. A first lateral distance between the bottom end of the floating gate and the erase gate may be larger than a second lateral distance between the top end of the floating gate and the erase gate.

Memory cells and methods of forming a memory cell

A method of forming a device including a SPAD detector and a BSI visible light sensor positioned on different planes, the device exhibiting improved resolution and pixel density are provided. Embodiments include a photodiode for detecting visible light; and a SPAD detector for detecting IR radiation, wherein the photodiode and the SPAD detector are on different planes.

Image sensor with stacked SPAD and method for producing the same

A method of forming a thick EG polysilicon over the FG and resulting device are provided. Embodiments include forming a CG on a substrate; forming an STI between a logic region and the CG; forming a polysilicon EG through the CG and CG HM; forming a polysilicon structure over the logic and STI; forming and overfilling with polysilicon a WL trench through the CG and CG HM, between the EG and STI; forming a buffer oxide in the polysilicon structure over the logic region and part of the STI; recessing the buffer oxide and etching back the polysilicon overfill down the CG HM; forming a second buffer oxide over the EG and logic region; recessing the WL polysilicon; removing the first and second buffer oxides; forming a mask with an opening over a center of the WL, the STI, and a majority of the logic region; and removing exposed polysilicon.

Method to form thicker erase gate poly superflash NVM

A memory device and a method of making the same are presented. The memory device includes a substrate and a memory cell formed on the substrate. The memory cell includes a single transistor. The single transistor includes a first gate on the substrate which functions as a control gate and a second gate embedded in the substrate which functions as a select gate.

Back-gated non-volatile memory cell

A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.

Method to tune narrow width effect with raised S/D structure

FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.

Growing community of inventors

Singapore, Singapore

Kian Ming Tan