Micron Technology Incorporated

Kian Chai Lee

Teck Kheng Lee

Wuu Yean Tay

Choon Kuan Lee

Cher Khng Victor Tan

Teck Poh

Sian Yong Khoo

Guek Har Lim

Thiam Chye Lim

Victor Cher Khng Tan

Yong Kian Tan

Kwang Hong Tan

Cheng Pour Poh

Kay Kit Tan

Chong Pei Andrew Lim

Yoke Kuin Tang

Cheng Poh Pour

Lien Wah Choong

Vijendran M

Vanessa Chong Hui Van

Teoh Bee Yong Tim

A semiconductor device assembly or package includes at least one semiconductor device that is positioned adjacent to floating leads. Such an assembly or package may include at least two semiconductor devices that face opposite directions from one another, with each being oriented such that bond pads thereof are at an opposite side of the assembly or package from bond pads of the other. Alternatively, an assembly or package may include a lead assembly with an internal portion, including one or more floating leads, and an external portion that are in planes that are offset relative to one another. Methods for designing lead frames, assemblies, and packages are also disclosed, as are assembly and packaging methods.

Balanced semiconductor device packages including lead frame with floating leads and associated methods

A method and apparatus for increasing the integrated circuit density in a flip-chip semiconductor device assembly including an interposer substrate facilitating use with various semiconductor die conductive bump arrangements. The interposer substrate includes a plurality of recesses formed in at least one of a first surface and a second surface thereof, wherein the recesses are arranged in a plurality of recess patterns. The interposer substrate also provides enhanced accessibility for test probes for electrical testing of the resulting flip-chip semiconductor device assembly.

Apparatus for flip-chip packaging providing testing capability

A method for designing a carrier substrate includes configuring at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. The method may also include configuring the carrier substrate to include one or more recessed areas that laterally surround at least a portion of the die-attach location to receive excess adhesive.

Methods for designing carrier substrates with raised terminals

An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with interconnections in the form of conductive bumps on both a first surface and a second surface to provide a respective first level interconnect and a second level interconnect for a semiconductor die to be mounted to the interposer substrate. The conductive bumps and conductive elements may be formed simultaneously by a plating process. The conductive bumps on the first surface are arranged to correspond with bond pads of a semiconductor die for the first level interconnect. The conductive bumps on the second surface are configured to correspond with a terminal pad pattern of a carrier substrate or other higher-level packaging.

Double bumping of flexible substrate for first and second level interconnects

Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.

BOC BGA package for die with I-shaped bond pad layout

A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. The solder may be positioned or formed on the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive excess adhesive.

Solder masks including dams for at least partially surrounding terminals of a carrier substrate and recessed areas positioned adjacent to the dams, and carrier substrates including such solder masks

A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive some of the excess adhesive. Assemblies and packages including one or both of the carrier substrate and solder mask are also disclosed, as are assembly methods and methods for designing the carrier substrate and solder mask.

Solder masks for use on carrier substrates, carrier substrates and semiconductor device assemblies including such solder masks, and methods

A method and apparatus for assembling semiconductor die-carrying interposer substrates in a stacked configuration. Each interposer substrate bears at least one die mounted by its active surface to a surface of the interposer substrate and wire bonded to terminals on the opposing substrate surface through an opening in the interposer substrate. Two interposer substrates are placed together with die-carrying sides outward and electrically connected with conductive elements extending transversely therebetween to form an interposer assembly, the interposer assembly bearing conductive elements extending transversely from one of the interposer substrates for connection to a carrier substrate. The space between the interposer substrates may be filled with a dielectric underfill material, as may the space between the interposer assembly and the carrier substrate to which the former is mounted.

Method for package reduction in stacked chip and board assemblies

An electronic device package having semiconductor die-carrying interposer substrates in a stacked configuration. Each interposer substrate bears at least one die mounted by its active surface to a surface of the interposer substrate and wire bonded to terminals on the opposing substrate surface through an opening in the interposer substrate. Two interposer substrates are placed together with die-carrying sides outward and electrically connected with conductive elements extending transversely therebetween to form an interposer assembly, the interposer assembly bearing conductive elements extending transversely from one of the interposer substrates for connection to a carrier substrate. The space between the interposer substrates may be filled with a dielectric underfill material, as may the space between the interposer assembly and the carrier substrate to which the former is mounted.

Apparatus for package reduction in stacked chip and board assemblies

Solder masks for use on carrier substrates, carrier substrates and semiconductor device assemblies including such solder masks

A method and apparatus for distributing a mold material in a mold for packaging microelectronic devices. In one embodiment, the microelectronic devices are placed on a substrate and the substrate is at least partially enclosed by the device region of a mold cavity. A mold material is passed along a flow axis through at least one entrance port into an intermediate region of the mold. The mold material is then passed from the intermediate region into the device region through a single opening spaced apart from and positioned between the entrance port and the microelectronic device. The single opening has a flow area transverse to the flow axis smaller than a flow area immediately upstream of the single opening to restrict the flow through the single opening. The mold material can accordingly form a uniform leading edge as it exits the opening and before it impinges on the microelectronic device.

Method and apparatus for distributing mold material in a mold for packaging microelectronic devices

A method and apparatus for assembling semiconductor die-carrying interposer substrates in a stacked configuration. Each interposer substrate bears at least one die mounted by its active surface to a surface of the substrate and wire bonded to terminals on the opposing substrate surface through an opening in the substrate. Two interposer substrates are placed together with die carrying sides outward and electrically connected with conductive elements extending transversely therebetween to form an interposer assembly, the interposer assembly bearing conductive elements extending transversely from one of the interposer substrates for connection to a carrier substrate. The space between the interposer substrates may be filled with a dielectric underfill material, as may the space between the interposer assembly and the carrier substrate to which the former is mounted.

Growing community of inventors

Singapore, Singapore

Kian Chai Lee