National University of Singapore

Chartered Semiconductor Manufacturing Ltd (corporation)

Kian Ann Ng

Yong Ping Xu

Chee Keong Tee

Chao Yuan

John Ho

Shih-Cheng Yen

Nitish V Thakor

Weng Hong Lai

Wang Wei Lee

In a described embodiment, a sensor-based communication apparatus () is disclosed. The communication apparatus () comprises a plurality of sensor nodes () associated with respective unique pulse signatures () and adapted to communicate with respective sensors () with each sensor () configured to generate a sensory signal () in response to a respective stimulus (). Each sensor node () is triggered, upon receipt of the corresponding sensory signal (), to transmit the associated unique pulse signature () independently and asynchronously through a transmission medium () shared by the sensor nodes (), and the unique pulse signatures () transmitted by the sensor nodes () being a representation () of a stimulus event associated with the stimuli detected by the corresponding sensors (). A method and a communication medium are also disclosed.

Sensor-based communication apparatus and method, and communication medium

A high CMRR neural signal amplifier is configured for supply rail common mode feedback (SR-CMFB) whereby a set of CMFB signals is provided to supply rails of front end LNAs. High CMRR is maintained through buffering outputs of front end signal LNAs and a reference LNA coupled to signal and reference inputs of second stage amplifiers, respectively; and buffering the reference LNA output using an active/guard buffer pair, whereby across a plurality of distinct multiplexing time intervals, during each multiplexing time interval one buffer of the pair functions as an active buffer that drives second stage amplifier reference inputs corresponding to second stage amplifier outputs being multiplexed to a set of multiplexor outputs, and the other buffer of the pair functions as a guard buffer coupled to other second stage amplifier reference inputs corresponding to second stage amplifier outputs not being multiplexed to the set of multiplexor outputs.

Multi-channel neural signal amplifier system providing high CMRR across an extended frequency range

Analog-to-digital converter (ADC) circuitry includes a first binary-weighted capacitor array having a total capacitance of 2C. The value of n represents number of bits of a digital signal that represents an analog signal. The ADC circuitry also includes a second binary-weighted capacitor array having a total capacitance of 2C. In addition to that, the ADC circuitry further includes a comparator circuit having first and second terminals. The first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array. The switching circuit within the second binary-weighted capacitor array may be configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array.

Symmetrical capacitor arrays succesive approximation register (SAR) analog-to-digital converter (ADC)

An antenna diode circuit for discharging static charge accumulated during wafer processing is described. The antenna diode circuit includes first and second junctions coupled to a circuit element and substrate. Between the first and second junctions is a diode circuit path with an antenna diode and at least one diode protection circuit coupled in series. The diode protection circuit reduces or prevents EOS current from flowing through the diode circuit path during an EOS event.

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Singapore, Singapore

Kian Ann Ng