International Business Machines Corporation

Infineon Technologies Ag

Other

Qimonda Ag

Kia-Seng Low

Gregory Costrini

John Patrick Hummel

Gill Yong Lee

Daniel C Edelstein

Richard Anthony Conti

David M Dobuzinsky

Alexander William Simpson

Peter Wrschka

Igor Kasko

Padraic C Shafer

Prakash Chimanlal Dev

Ravikumar Ramachandran

David Lee Rath

Michael C Gaidis

Wolfgang Raberg

Mahadevaiyer Krishnan

Xian Jay Ning

Arunava Gupta

Rajiv M Ranade

Walter Glashauser

Greg Costrini

Joachim Nuetzel

Ihar Kasko

George Stojakovic

Frank Findeis

A method of forming a magnetic switching device is provided. The method includes depositing a bilayer hardmask, which may comprise a first mask layer of titanium nitride with a second mask layer of tungsten formed thereon. A first lithography process is performed to pattern the second mask layer, and a second lithography process is performed to pattern the first mask layer. Thereafter, the magnetic tunnel junction stack may be patterned in accordance with the first mask layer. An etching process may be performed to further pattern the first mask layer in accordance with the second mask layer. An optional passivation layer may be formed over the first mask layer and the second mask layer.

Magnetic switching device

The invention relates to a method of encapsulating conductive lines of semiconductor devices and a structure thereof. An encapsulating protective material, such as TaN, Ta, Ti, TiN, or combinations thereof is disposed over conductive lines of a semiconductor device. The encapsulating protective material protects the conductive lines from harsh etch chemistries when a subsequently deposited material layer is patterned and etched. The encapsulating protective material is conductive and may be left remaining in the completed semiconductor device. The encapsulating material is patterned using a masking material, and processing of the semiconductor device is then continued. The masking material may be left remaining in the structure as part of a subsequently deposited insulating material layer.

Encapsulation of conductive lines of semiconductor devices

A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.

Spacer integration scheme in MRAM technology

Self-aligning vias and trenches etched between adjacent lines of metallization allows the area of the dielectric substrate allocated to the via or trench to be significantly reduced without increasing the possibility of electrical shorts to the adjacent lines of metallization.

Self-aligned mask to reduce cell layout area

Magnetic tunnel junction devices can be fabricated using a two-step deposition process wherein respective portions of the magnetic tunnel junction stack are defined independently of one another.

Two-step magnetic tunnel junction stack deposition

A method of manufacturing a resistive semiconductor memory device (), comprising depositing an insulating layer () over a workpiece (), and defining a pattern for a plurality of alignment marks () and a plurality of conductive lines () within the insulating layer (). A conductive material is deposited over the wafer to fill the alignment mark () and conductive line () patterns. The insulating layer () top surface is chemically-mechanically polished to remove excess conductive material from the insulating layer () and form conductive lines (), while leaving conductive material remaining within the alignment marks (). A masking layer () is formed over the conductive lines (), and at least a portion of the conductive material is removed from within the alignment marks (). The alignment marks () are used for alignment of subsequently deposited layers of the resistive memory device ().

MRAM MTJ stack to conductive line alignment method

A semiconductor device () and method of fabrication thereof, wherein a plurality of conductive lines () are formed over a workpiece, a surface-smoothing conductive material () is disposed over the conductive lines (), and a magnetic material () disposed is over the surface-smoothing conductive material (). The surface-smoothing conductive material () has a smaller grain structure than the underlying conductive lines (). The surface-smoothing conductive material () is polished so that the surface-smoothing conductive material () has a texturally smoother surface than the surface of the conductive lines ().

Method of forming surface-smoothing layer for semiconductor devices with magnetic material layers

A method for manufacturing a magnetoresistive random access memory (MRAM) cell is disclosed, which alleviates the problem of Neel coupling caused by roughness in the interface between the tunnel junction layer and the magnetic layers. The method includes depositing first and second barrier layers on the conductor, wherein the first barrier layer has a polish rate different from that of the second barrier layer. The second barrier layer is then essentially removed by chemical mechanical polishing (CMP), leaving a very smooth and uniform first barrier layer. When the magnetic stack is then formed on the polished first barrier layer, interfacial roughness is not translated to the tunnel junction layer, and no corruption of magnetization is experienced.

Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology

A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates

A semiconductor device ( ) and method of fabrication thereof, wherein a plurality of first conductive lines ( ) are formed in a dielectric layer ( ) over a substrate ( ), and an insulating cap layer ( ) is disposed over the first conductive lines ( ) and exposed portions of the dielectric layer ( ). The insulating cap layer ( ) is patterned and etched to expose stack portions of the first conductive lines ( ). A conductive cap layer ( ) is deposited over the exposed portions of the first conductive lines ( ). A magnetic material stack ( ) is disposed over the insulating cap layer ( ), and the magnetic material stack is etched to form magnetic stacks. The insulating cap layer ( ) and conductive cap layer ( ) protect the underlying first conductive line ( ) material during the etching processes.

Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers

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Hopewell Junction, NY, United States of America

Kia-Seng Low