Samsung Electronics Co., Ltd.

Ki-Young Lee

Sang-Hoon Park

Seung-Han Park

Dong-Gi Choi

Yeong-Kyeong Seong

Ja-Young Choi

Kwang-Dong Yoo

Disclosed are an apparatus and a method for determining lesion similarity of a medical image. The apparatus for determining lesion similarity according to one aspect of the present invention may comprise: an image input unit for receiving a reference image comprising a reference lesion area, and a target image comprising a target lesion area; and a similarity determination unit for determining similarity of the reference lesion area and the target lesion area by applying an advantage weight, which increases as getting closer to the center of the reference lesion area, to pixels included in a first area of the reference lesion area, and a penalty weight, which increases as getting farther away from the reference lesion area, to pixels included in a second area of the target lesion area.

Apparatus and method for determining lesion similarity of medical image

In a semiconductor device and a method of fabricating the same, a fuse and a capacitor are formed at a same level on a semiconductor substrate having a fuse area and a capacitor area. The fuse is placed on the fuse area, and a lower plate is placed on the capacitor area. The lower plate is located on a same plane as the fuse. Further, an upper plate is located above the lower plate, and a capping layer is interposed between the lower plate and the upper plate. Therefore, the fuse and the capacitor can be formed at the same time, thereby minimizing photolithography and etch process steps.

Semiconductor device having fuse and capacitor at the same level and method of fabricating the same

A semiconductor device having an analog capacitor and a method of fabricating the same are disclosed. The semiconductor device includes a bottom plate electrode disposed at a predetermined region of a semiconductor substrate, and an upper plate electrode having a region overlapped with the bottom plate electrode thereon. The upper plate electrode and the bottom plate electrode are formed of a metal compound. A capacitor dielectric layer is interposed between the bottom plate electrode and the upper plate electrode. A bottom electrode plug and an upper electrode plug are connected to the bottom plate electrode and the upper plate electrode through the interlayer dielectric layer.

Semiconductor device with analog capacitor and method of fabricating the same

Semiconductor devices with copper interconnections and MIM capacitors and methods of fabricating the same are provided. The device includes a lower electrode composed of a first copper layer. A first insulation layer covers a lower electrode. A window is formed in the first insulation layer to expose a portion of the lower electrode. A capacitor includes a lower barrier electrode, a dielectric layer, and an upper barrier electrode, which are sequentially formed to cover a sidewall and a bottom of the window. An intermediate electrode composed of a second copper layer fills a remaining space of an inside of the capacitor. A second insulation layer is formed on the intermediate electrode. A connection hole is formed in the second insulation layer to expose a portion of the intermediate electrode. A connection contact plug composed of a third copper layer fills the connection hole. An upper layer composed of a fourth copper layer is formed on the connection contact plug to be connected to the connection contact plug.

Semiconductor devices with capacitors of metal/insulator/metal structure and methods for forming the same

A method for forming a fuse includes forming an interconnection pattern and a fuse pattern on a substrate using a damascene process. A passivation layer is formed on a surface of the substrate over the interconnection pattern and the fuse pattern. Then, the passivation layer is patterned to form a pad opening that exposes a portion of the interconnection pattern. A metal pad is formed on the interconnection pattern in the pad opening. A portion of the metal pad extends over the passivation layer. The passivation layer on the fuse pattern is partially etched to form a fuse opening.

Method for forming fuse integrated with dual damascene process

An integrated circuit includes first and second diodes that are electrically connected to a conductive line in antiparallel, to dissipate both positive and negative charges on the conductive line during plasma processing. The integrated circuit also includes a fuse for disconnecting one of the first and second diodes from the conductive line after the plasma processing, to thereby allow conduction of one of positive and negative charge on the conductive line after the plasma processing. Accordingly, integrated circuits are fabricated by forming a conductive line on an integrated circuit substrate and first and second diodes in the integrated circuit substrate that are electrically connected to the conductive line in antiparallel. Then, plasma processing is performed on the integrated circuit substrate including the conductive line and the first and second diodes, such that the first and second diodes dissipate both positive and negative charges on the conductive line during the plasma processing. Then, one of the first and second diodes is disconnected from the conductive line after performing the plasma processing, to thereby allow conduction of one of positive and negative charge on the conductive line after performing the plasma processing.

Methods for fabricating integrated circuit devices using antiparallel diodes to reduce damage during plasma processing

Methods for manufacturing semiconductor devices are provided. First and second portions of a first metal layer are formed in a first interlayer insulating layer. A second interlayer insulating layer is formed to cover the first portion and has an opening that exposes the second portion. A dielectric layer is formed on the exposed second portion. A second metal layer is formed on the dielectric layer to fill the opening in a capacitor region. A via contact hole to expose the first portion is formed in the second insulating layer. A third metal layer is formed in the via contact hole. A third interlayer insulating layer is formed on the second interlayer insulating layer. Contact holes to expose the second metal layer and the third metal layer are formed in the third interlayer insulating layer. A fourth metal layer is formed in the contact holes.

Method for manufacturing semiconductor device having capacitor and via contact

A method for fabricating a MIM capacitor of a MDL logic or analog circuit of a semiconductor device. A conductivity layer is formed on a semiconductor substrate having a first inter-level insulating layer. A capping metal layer having an etching rate higher than an oxide layer is formed on the conductivity layer. A lower electrode comprising a &ldquo;conductivity layer/capping metal layer&rdquo; deposition is formed by selectively etching the capping metal layer and the conductivity layer in order to expose a predetermined part of the surface of the first inter-level insulating layer. A second inter-level insulating layer is formed on the first inter-level insulating layer covering the lower electrode. A via hole is formed by selectively etching both the second inter-level insulating layer and the lower electrode thereby to expose a portion of the lower electrode so that a tapered capping metal layer remains along the lower edges of the via hole. A dielectric layer, devoid of step coverage defects and concentrated electric fields, is inserted in the via hole between the lower and upper electrodes thereby preventing current leakage and short circuits at portions of the dielectric layer. This has the beneficial effect of substantially improving product yield and reliability.

Method for fabricating an integrated circuit capacitor

Integrated circuit devices that use antiparallel diodes to reduce damage during plasma processing

A method for forming an integrated circuit device includes the steps of forming a first capacitor electrode on a substrate and forming a first wiring electrode on the substrate. An insulating layer is formed on the first capacitor electrode and on the first wiring electrode opposite the substrate. A second capacitor electrode is formed on a portion of the insulating layer opposite the first capacitor electrode. A contact hole is formed in the insulating layer exposing a portion of the first wiring electrode. A second wiring electrode is then formed on the exposed portion of the wiring electrode, after forming the second capacitor electrode. Related structures are also discussed.

Growing community of inventors

Kyunggi-do, South Korea

Ki-Young Lee