Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Ki-Yeup Lee

Shin-Il Choi

Dong-Ju Yang

Yu-Gwang Jeong

Sang-Gab Kim

Jean-Ho Song

Hong-Kee Chin

Shi-Yul Kim

Seung-Ha Choi

Yun-Jong Yeo

Jae-Hong Kim

Byeong-Beom Kim

Ji-Young Park

Ki-Yong Song

Dong-Gyu Kim

Chang-Oh Jeong

Jong-in Kim

Bong-Kyun Kim

Jong-Hyun Choung

Joo-han Kim

Jae-Hyoung Youn

Sun-Young Hong

Sung-Ryul Kim

Yang-Ho Bae

Hee-Joon Kim

Hwa-Yeul Oh

Yeo-Geon Yoon

Chang-Hoon Kim

Jung-Suk Bang

Woo-Sung Sohn

O-Sung Seo

Je-Hyeong Park

Nam-Seok Suh

Pil-Soon Hong

Sung-Hen Cho

Dong-Hoon Lee

Min-Seok Oh

Yong-Hwan Kim

Yoon-Ho Kang

Tae-Woo Kim

Yu Gwang Jeong

A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Thin film transistor substrate and the method thereof

A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.

Contact portion of wire and manufacturing method thereof

A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer.

Thin film transistor array panel and method for manufacturing the same

A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

Method of fabricating a thin film transistor array substrate

The present invention relates to a liquid crystal display, wherein arrangement of liquid crystal molecules thereof is controlled by using a monomer that is polymerized by ultraviolet rays to provide a pre-tilt. To prevent damage to organic material layers when irradiating ultraviolet rays to the monomer, a blocking film made of an ultraviolet absorbing agent is formed on or over at least one such layer.

Liquid crystal display and manufacturing method thereof

A method for manufacturing a thin film transistor array panel includes forming a gate line; forming an insulating layer on the gate line; forming first and second silicon layers first and second metal layers; forming a photoresist pattern having first and second portions; forming first and second metal patterns by etching the first and second metal layers; processing the first metal pattern with SFor SF/He; forming silicon and semiconductor patterns by etching the second and first silicon layers; removing the first portion of the photoresist pattern; forming an upper layer of a data wire by wet etching the second metal pattern; forming a lower layer of the data wire and an ohmic contact by etching the first metal and amorphous silicon patterns; forming a passivation layer including a contact hole on the upper layer; and forming a pixel electrode on the passivation layer.

Method for manufacturing thin film transistor array panel

A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.

A metal wiring layer and a method of fabricating the metal wiring layer are provided. The method includes forming a dielectric layer on a substrate, forming a plurality of dielectric layer patterns and holes therein on the substrate by etching part of the dielectric layer, with a cross sectional area of the holes in the dielectric layer patterns decreasing with increasing distance away from the substrate and the holes exposing the substrate, forming a trench by etching a portion of the substrate exposed through the holes in the dielectric layer patterns, and forming a metal layer which fills the trench and the holes in the dielectric layer patterns. Thus, it is possible to prevent the occurrence of an edge build-up phenomenon by forming a metal layer in a plurality of holes in the dielectric layer patterns having a cross sectional area decreasing with increasing distance away from the substrate. Therefore, it is possible to prevent the transmittance of a liquid crystal layer from decreasing due to a failure to properly fill liquid crystal molecules in the liquid crystal layer, and thus to increase the quality of display.

Metal wiring layer and method of fabricating the same

After forming a signal line including aluminum, an upper layer of an oxide layer including aluminum that covers the signal line is formed in the same chamber and by using the same sputtering target as the signal line, or a buffer layer of an oxide layer including aluminum is formed in a contact hole exposing the signal line during the formation of the contact hole. Accordingly, the contact characteristic between an upper layer including indium tin oxide ('ITO') or indium zinc oxide ('IZO') and the signal line may be improved to enhance the adhesion therebetween while not increasing the production cost of the thin film transistor (&#x201c;TFT&#x201d;) array panel.

Thin film transistor panel and method of manufacturing the same

Growing community of inventors

Yongin-si, South Korea

Ki-Yeup Lee