Samsung Electronics Co., Ltd.

Db Hitek Co., Ltd.

Ki-Won Lim

Byung-Gil Choi

Young-ran Kim

Won-ryul Chung

Woo-Yeong Cho

Du-Eung Kim

Kwang-Jin Lee

Ki-sung Kim

Hye-jin Kim

Eui-Gyu Han

Jeong-Un Choi

In-Cheol Shin

Chang-han Choi

Jin-Hyo Jung

Young-Ran Kim

Seung-Hyun Eom

Hae-Taek Kim

Ja-Geon Koo

Moon-Ki Jung

Hyun-Joong Lee

Sang-Yong Lee

Won-Ryul Chung

Provided is an RF switch device () in which body contact regions () are formed at respective positions adjacent to or partially overlapping opposite ends of a gate region () so that holes in a body of the device can escape or flow in either or both of two directions, rather than in only a single direction.

RF switch device

A method for testing a nonvolatile memory device includes: monitoring a first resistance dispersion and a second resistance dispersion of a nonvolatile memory device, determining a lower test bias level and an upper test bias level that are disposed on opposite sides of a reference bias level, calculating the number of first fail bits generated in the first resistance dispersion based on the lower test bias level and the number of second fail bits generated in the second resistance dispersion based on the upper test bias level, determining a selected reference bias level using the number of the first fail bits and the number of the second fail bits, and trimming the reference bias level to the selected bias level.

Nonvolatile memory device and method for testing nonvolatile memory device using variable resistance material

A phase-change memory device and its firing method are provided. The firing method of the phase-change memory device includes applying a writing current to phase-change memory cells, identifying a state of the phase-change memory cells after applying the writing current, and applying a firing current, in which an additional current is added to the writing current, to the phase-change memory cells in accordance with the state.

Phase-change memory device

Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array. This stair-step sequence of at least two unequal bit line voltages includes a precharge voltage (e.g., Vcc-Vth) at a first step and a higher boosted voltage (e.g., Vpp-Vth) at a second step that follows the first step.

Nonvolatile memory devices having variable-resistance memory cells and methods of programming the same

Phase-change memory device and firing method for the same

Nonvolatile memory devices include a plurality of nonvolatile memory cells and a write circuit that is operable to write data to the nonvolatile memory cells over a plurality of consecutive division write periods by generating a plurality of write pulses whose peaks do not coincide with one another to the nonvolatile memory cells.

Nonvolatile memory devices that include a write circuit that writes data over multiple write periods using pulses whose peaks do not coincide with each other

A PRAM includes a memory cell array of phase change memory cells, and a write circuit receiving an externally provided first voltage and supplying a write pulse for writing data to the memory cells in a normal operation mode. The write circuit also receives an externally provided second voltage higher than the first voltage and supplies a firing pulse to at least one firing-failed phase change memory cell.

PRAM and method of firing memory cells

Integrated circuit devices include a comparator circuit and a fuse programmable input circuit. The fuse programmable input circuit generates first and second differential input signals at voltage levels that can be controlled through a pair of fuses. The comparator circuit generates an output signal based on the relative voltage levels exhibited by the first and second differential input signals. In particular, the output signal is driven to a first logic state when the voltage difference between the first and second differential input signals is positive and the output signal is driven to a second logic state, which is opposite the first logic state, when the voltage difference is negative. Because the comparator is responsive to the relative difference between the voltage levels of the first and second differential input signals and not the absolute magnitudes of the voltage levels, fuse remnants that may exist after the fuse programmable input circuit has been programmed (i.e., one or more fuses have been cut) typically do not affect the output signal.

Integrated circuit devices using fuse elements to generate an output signal that is independent of cut fuse remnants

Growing community of inventors

Suwon-si, South Korea

Ki-Won Lim