Skhynix Inc.

Other

Samsung Electronics Co., Ltd.

Hyundai Motor Company

Kia Motors Corporation

Hynix Semiconductor Inc.

Kia Corporation

Ki Won Lee

Joon Young Park

Jung Hyuk Yoon

Seung Jun Bae

Yong Cheol Bae

Tae Yong Lee

Hyung Dong Lee

Seok Man Hong

Jin Su Park

Jae Hyun Park

Jeen Park

Jang Ho Kim

Hyo Jin Lee

Yong Jin Kwon

Hyuck Sang Yim

Ki Myung Kyung

Je Hyun Lee

Jun Haeng Heo

Ho Shin Lee

Yung Kwan Kim

Jung Sic Sung

Woo Hyuk Jang

Ki Young Lim

Jae Keun Jeon

Yul Ji Chang

Yeo Rok Yoon

Hey Young Park

Seoung Ju Chung

Jong Yeol Choi

Jong Kyu Bae

A vehicle controller and a method thereof are provided. The vehicle controller includes a processor that determines whether a driver has an intention to make a lane change using at least one of a steering angle condition, a gaze condition of the driver, or a driving pattern condition of the driver. The processor shares lane change information with a surrounding vehicle, when it is determined that the driver has the intention to make the lane change. The controller also has a storage storing data and an algorithm run by the processor.

Vehicle controller and method thereof

The application relates to an exercise history managing device. In one aspect, the device includes a map data providing unit configured to provide, to a user terminal, map data about a specific area requested by the user terminal. The device may also include a user relation managing unit configured to manage a relationship between each user and the other users. The device may further include an exercise information managing unit configured to receive information about at least one of an exercise name that is input through the user terminal, a first category obtained by classifying exercises belonging to each exercise name according to a first condition, a second category obtained by classifying an exercise belonging to the first category according to a second condition, and a specific exercise belonging to the second category, store the information, and retrieve exercise information in response to a request from the user terminal.

Exercise history managing device, exercise history managing method, and computer program for executing same in computer

A method for controlling a semi-active engine mount is provided to increase both NVH performance and driving performance of a vehicle and reduce noise and vibration generated under specific driving conditions. The method includes storing real-time vehicle speed data at intervals of a predetermined time and determining whether an engine is in an idling state. In response to determining that the engine is in the idling state, determining whether a current driving state of the vehicle corresponds to predetermined conditions in which noise and vibration performance is prioritized based on vehicle speed change information. The semi-active engine mount is adjusted to be in an on state, upon determining that the current driving state of the vehicle in the idling state of the engine corresponds to the predetermined conditions.

Method and system for controlling semi-active engine mount

A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.

Variable resistive memory device and method of driving a variable resistive memory device

A variable resistive memory device includes a memory cell array and a control circuit block. The memory cell array includes a plurality of memory cells that are connected between a global word line and a global bit line. The control circuit block is positioned on at least one of edge portions of the memory cell array. The memory cell array is classified into a first group with the memory cells that are adjacent to the control circuit block and a second group with the memory cells that are remote in relation to the control circuit block. The second group is farther from the control circuit block than the first group. The control circuit block includes a write control unit that generates a control signal for writing on the memory cell in the first group in a different way compared to writing on the memory cell in the second group.

Variable resistive memory device and method of operating the same

A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.

Variably resistive memory device

A resistance variable memory device may include a plurality of memory cells and a control circuit block. The memory cells may be connected between a global word line and a global bit line. The control circuit block may control the memory cells. The control circuit block may include a write pulse control block. The write pulse control block may include a high resistance path circuit and a bypass circuit connected between the global word line and a selected memory cell. The write pulse control block may selectively enable any one of the high resistance path circuit and the bypass circuit in accordance with a position the selected memory cell.

Resistance variable memory device

A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.

Semiconductor system, semiconductor chip, and semiconductor memory system including the semiconductor system

An embodiment of the present invention discloses an exercise measuring device attachable to and detachable from a bar of an exercise apparatus, the exercise measuring device including: a main body; a coupling portion formed on the main body and configured to be coupled to at least an end portion of the bar; and a reader formed on the main body, wherein when a weight portion including a tag is fitted to the end portion of the bar, the reader detects a weight of the weight portion fitted to the bar by reading the tag of the weight portion.

Exercise measuring device, exercise apparatus having same, and exercise measuring method

A data processing system includes a host device; and a data storage device suitable for detecting a voltage drop state in the voltage received from the host device, changing a first key received from the host device to a second key when detecting the voltage drop state, generating a cyclical redundancy check (CRC) data based on the second key, and transmitting the generated CRC data to the host device.

Data storage device and data processing system

A fitness structure includes a bar having a first end portion and a second end portion, a pair of bar support portions provided at each side of the bar and having a plurality of bar support members to place the bar at a plurality of heights, a first load portion and a second load portion spaced apart from the bar to a certain degree and facing each other, a first cable coupled between the first end portion of the bar and the first load portion, a second cable coupled between the second end portion of the bar and the second load portion. Heights of the first load portion and the second load portion vary depending on a height of one of the plurality of bar support members at which the bar is detachably placed.

Fitness structure

A server is provided comprising a processor configured to: receive an indication of a location of a first device that is subscribed to a disaster notification service; in response to receiving a disaster alert, detect that the first device is located in an area associated with the disaster based on the indication of the location of the first device; identify a second device that has registered the first device as a friend; and transmit a first indication of the disaster to the first device and a second indication of the disaster to the second device.

Method and apparatus for disaster notification

A method of operating a memory controller includes: receiving a data signal from a memory device, wherein the data signal has an output high level voltage (VOH); determining a reference voltage according to the VOH; and comparing the data signal with the reference voltage to determine a received data value, wherein the VOH is proportional to a power supply voltage (VDDQ).

Growing community of inventors

Cheongju-si, South Korea

Ki Won Lee