Samsung Electronics Co., Ltd.

Skhynix Inc.

Ki-Vin Im

Jong-Cheol Lee

Jae-Hyun Yeo

Hoon-Sang Choi

Han-jin Lim

Young-sun Kim

Sung-Tae Kim

Ki-yeon Park

Sang-yeol Kang

In-seak Hwang

Cha-Young Yoo

In-Sung Park

Eun-ae Chung

Sang-Yeol Kang

Young-kyu Cho

Yong-hee Choi

Ki-Hyun Kim

Youn-soo Kim

Jae-Young Park

Ki-Yeon Park

Se-hoon Oh

Young-kuk Kim

Yong-Woo Hyung

Won-Jun Jang

Sung-hae Lee

Se-Hun Kang

Jun-noh Lee

Han-Joon Kim

Moon-Hyeong Han

Eun-Ae Chung

Seung-Hwan Lee

Seok-Jun Won

Ki-chul Kim

In-Sun Park

Dong-Hyun Im

Hyeon-Deok Lee

Jin-il Lee

Jun-Seok Lee

Seok-Woo Nam

Yun-Jung Lee

Kong-Soo Lee

Young-Sun Kim

Byoung-ho Kwon

Young-Geun Park

Kwang-Hee Lee

Hyun-jun Kim

Jong-Bom Seo

Jung-Hwan Oh

Kyoung-Ryul Yoon

Jong-cheol Lee

Jin-Woo Bae

Jae-hyun Yeo

Hye-sung Park

Young-Sub You

Jong-hyuk Park

Hee-sook Cheon

Kil-chul Kim

Hoon-sang Choi

Won-Shik Shin

Hun-Young Lim

Jin-Won Ma

A semiconductor device includes: a first electrode; a second electrode; and a multi-layered stack including a hafnium oxide layer of a tetragonal crystal structure which is positioned between the first electrode and the second electrode, wherein the multi-layered stack includes: a seed layer for promoting tetragonal crystallization of the hafnium oxide layer and having a tetragonal crystal structure; and a booster layer for boosting a dielectric constant of the hafnium oxide layer.

Semiconductor device with a booster layer and method for fabricating the same

A semiconductor device having a capacitor includes a substrate which has a transistor, a first insulating pattern which is formed on the substrate and does not overlap a first contact node formed in the substrate, a second insulating pattern which is formed on the substrate, does not overlap a second contact node formed in the substrate, and is separated from the first insulating pattern, a first lower electrode which is formed on part of the substrate and sidewalls of the first insulating pattern, a second lower electrode which is formed on part of the substrate and sidewalls of the second insulating pattern, a dielectric layer pattern which is formed on the first lower electrode and the second lower electrode, and an upper electrode which is formed on the dielectric layer pattern. Related fabrication methods are also discussed.

Semiconductor device having capacitor and method of fabricating the semiconductor device

Semiconductor devices and fabricating methods thereof are provided. A semiconductor device may include a substrate, a metal layer on the substrate, a seed layer on the metal layer, a nanowire including a pillar shape on the seed layer, a dielectric film conformally covering the nanowire, and an electrode film on the dielectric film.

Semiconductor devices including nanowire capacitors and fabricating methods thereof

Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a storage electrode having a cylinder shape, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film, wherein the plate electrode includes a first semiconductor compound layer and a second semiconductor compound layer sequentially stacked one on the other, and the first semiconductor compound layer has a crystallinity different from that of the second semiconductor compound layer.

Semiconductor device and fabricating method thereof

A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.

Methods of fabricating semiconductor devices

A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.

Semiconductor devices having self-aligned contact pads

Methods of manufacturing semiconductor devices having self-aligned contact pads

A semiconductor device may include a semiconductor substrate and a plurality of first capacitor electrodes arranged in a plurality of parallel lines on the semiconductor substrate with each of the first capacitor electrodes extending away from the semiconductor substrate. A plurality of capacitor support pads may be provided with each capacitor support pad being connected to first capacitor electrodes of at least two adjacent parallel lines of the first capacitor electrodes and with adjacent capacitor support pads being spaced apart. A dielectric layer may be provided on each of the first capacitor electrodes, and a second capacitor electrode may be provided on the dielectric layer so that the dielectric layer is between the second capacitor electrode and each of the first capacitor electrodes. Related methods are also discussed.

Semiconductor devices including capacitor support pads

Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.

Semiconductor device including insulating layer of cubic system or tetragonal system

An atomic layer deposition apparatus and an atomic layer deposition method increase productivity. The atomic layer deposition apparatus includes a reaction chamber, a heater for supporting a plurality of semiconductor substrates with a given interval within the reaction chamber and to heat the plurality of semiconductor substrates and a plurality of injectors respectively positioned within the reaction chamber and corresponding to the plurality of semiconductor substrates supported by the heater. The plurality of injectors are individually swept above the plurality of semiconductor substrates to spray reaction gas.

Atomic layer deposition apparatus

Methods of manufacturing semiconductor devices including multilayer dielectric layers are disclosed. The methods include forming a multilayer dielectric layer including metal atoms and silicon atoms on a semiconductor substrate. The multilayer dielectric layer includes at least two crystalline metal silicate layers having different silicon concentrations. The multilayer dielectric layer may be used, for example, as a dielectric layer for a capacitor, or as a blocking layer for a nonvolatile memory device.

Methods of fabricating semiconductor devices including multilayer dielectric layers

Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing the chemical solvent from the surface of the semiconductor substrate.

Methods of removing water from semiconductor substrates and methods of depositing atomic layers using the same

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Seongnam-si, South Korea

Ki-Vin Im