Samsung Electronics Co., Ltd.

Korea Institute of Construction Technology

Ki-Tae Park

Yeong-taek Lee

Jung-Dal Choi

Ki-Nam Kim

Doo-Gon Kim

Jae-Yong Jeong

Kang-Wook Lee

Myung-Hoon Choi

Hyun-Kyoung Kim

Jong-Sun Sel

Yoo-Cheol Shin

Sung-Kyu Jo

Uk-Jin Roh

Yong-Seok Kim

Young-Don Choi

Dong-Hun Kwak

Min-Seok Kim

Yun-sang Lee

Bo-Geun Kim

Jae-Woo Im

Soon-Wook Hwang

Yeong-Taek Lee

Hyun-Jun Yoon

Tae-young Kim

Young-Ho Lim

Jung-Hoon Park

Hyun-Wook Wook Park

Doohyun Kim

Chang-Sub Lee

Sung-soo Lee

Sangyong Yoon

Yoon-Hee Choi

Bong-Soon Lim

Young-Ho Lee

Hongrak Son

Sang-won Shim

Kyung-Ryun Kim

Jae-Sung Sim

Hyun Jun Yoon

Dong-kyo Shim

Pan-Suk Kwak

Chul-Jin Hwang

Myoung-gon Kang

Young-Wook Jeong

Yoon-Koog Hwang

Hyeong-Yeol Kim

Sun-Myung Kim

Doo-gon Kim

Myoung-Hoon Choi

Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.

Flash memory devices having three dimensional stack structures and methods of driving same

A memory diagnosis system includes a memory device and a server. The memory device includes a memory module configured to adjust operational parameters in response to a parameter control signal, a memory controller configured to generate the parameter control signal in response to a feedback signal, and a memory state monitor configured to monitor the memory module to generate an information signal that includes information on a state of the memory module. The server is configured to generate the feedback signal in response to the information signal.

Memory diagnosis system

Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.

Programming method for non-volatile memory device

A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

Stacked semiconductor apparatus, system and method of fabrication

A non-volatile memory device includes a substrate, a memory cell array on the substrate, a plurality of bonding pads, and a pad circuit. The memory cell array includes a plurality of gate conductive layers stacked on the substrate in a vertical direction and a plurality of channels penetrating into the plurality of gate conductive layers on an upper portion of the substrate. The plurality of bonding pads are on at least part of an upper portion of the memory cell array. The plurality of bonding pads are configured to electrically connect the non-volatile memory device to an external device. The pad circuit is between the substrate and the memory cell array. The pad circuit is electrically connected to at least one of the plurality of bonding pads.

Non-volatile memory device

A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation.

Memory device, memory system, and method of controlling read voltage of the memory device

A non-volatile memory device receives a start command through a command line, receives an address through an address line, receives at least one setting value through the address line, receives a confirm command corresponding to the start command through the command line, sets at least one parameter of the non-volatile memory device as the setting value based on the start command, a number of the setting value, and the confirm command, and executes an operation that corresponds to the start command, on a memory cell that corresponds to the address, based on the set parameter.

Non-volatile memory device and related method of operation

A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias.

Programming nonvolatile memory device using program voltage with variable offset between programming state distributions

A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage.

Method of operating memory device

A memory device useable with a memory system includes a voltage generator to a plurality of first candidate voltages and a plurality of second candidate voltages, and an X decoder to sequentially apply each of the plurality of first candidate voltages and each of the plurality of second candidate voltages to one or more cells of a memory cell array, and then to apply one of the plurality of first candidate voltages and one of the plurality of second candidate voltages as a first read voltage and a second voltage, respectively, to read data from the cells of the memory cell array according to a characteristic of the cells of the memory cell array.

Apparatus and method of operating memory device

A method of driving a nonvolatile memory device, includes; forward shifting threshold voltages of nonvolatile memory cells by executing a first program loop with respect to the nonvolatile memory cells, and thereafter, reverse shifting the threshold voltages of the nonvolatile memory cells, and again forward shifting the threshold voltages of the nonvolatile memory cells by executing a second program loop with respect to the nonvolatile memory cells.

Method of driving nonvolatile memory devices

A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips

Semiconductor memory device including plurality of memory chips

A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.

Multi-bit flash memory device and memory cell array

A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region.

Semiconductor device having through electrode and method of fabricating the same

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Seongnam-si, South Korea

Ki-Tae Park