Samsung Electronics Co., Ltd.

Ki-Seok Oh

Yeon-Kyu Choi

Kyung-Soo Ha

Seok-Hun Hyun

Chang-Kyo Lee

Dae-Sik Moon

Jung-Hwan Choi

Gil-Hoon Cha

Young-Soo Sohn

Seung-Jun Shin

Hye-Ran Kim

Donghun Lee

Changkyo Lee

Young-Hoon Son

Jin-Hoon Jang

Hyun-Yoon Cho

Daesik Moon

Seokhun Hyun

Youngjin Cho

Jong-Hyun Choi

Insu Choi

Sun-Young Lim

Seong-Hwan Jeon

Sungyong Seo

Joon-Young Park

Dong-Yang Lee

Young-Sun Min

Kwanghyun Kim

Yong-cheol Bae

Yong-Gwon Jeong

Jonghyun Choi

Seong-Heon Yu

Doo-Hee Hwang

Dongwoo Sohn

Yong-Hun Ahn

An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.

Semiconductor memory device, electronic device and method for setting the same

A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Memory device, memory system, and operation method of memory device

A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Memory device adjusting duty cycle and memory system having the same

A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Method and memory system for optimizing on-die termination settings of multi-ranks in a multi-rank memory device

A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Memory device having a plurality of low power states

An electronic device includes: a system-on-chip (SoC) including a processor, a near-memory controller controlled by the processor, and a far-memory controller controlled by the processor; a near-memory device including a first memory channel configured to communicate with the near-memory controller and operate in a first mode of a plurality of modes, and a second memory channel configured to communicate with the near-memory controller and operate in a second mode different from the first mode from among the plurality of modes; and a far-memory device configured to communicate with the far-memory controller. The first memory channel is further configured to, based on a command from the near-memory controller, change an operation mode from the first mode to the second mode.

Electronic device including near-memory supporting mode setting, and method of operating the same

A memory module including at least one memory and a memory control circuit to control the at least one memory and to generate an internal operation request including an information regarding internal operation time when the memory module need the internal operation time. The memory control circuit is to transfer the internal operation request to an external device, to receive a first command from the external device in response to the internal operation request and including an information of whether the internal operation time is approved, and to perform the internal operation during the internal operation time based on the first command.

Memory module and memory system relating thereto

Growing community of inventors

Seoul, South Korea

Ki-Seok Oh