Samsung Electronics Co., Ltd.

Ki-Seok Lee

Chan-Sic Yoon

Yoo-Sang Hwang

Je-min Park

Bong-Soo Kim

Sung-Hee Han

Dae-Ik Kim

Sin-Seok Seo

Do-Hy Hong

Hui-Jung Kim

Dae-Kyu Choi

Ji-Young Kim

Eun-Jung Kim

Chang-Hyun Cho

Ho-in Ryu

Hyeon-Ok Jung

Bomg-Soo Kim

Dong-oh Kim

Yong-Seok Park

Jung-Hyun Kim

Je-Min Park

Ho-in Lee

Yong-kwan Kim

Myeong-Dong Lee

Se-Myeong Jang

Sung-Ho Jang

Kyu-Hyun Lee

Augustin Jinwoo Hong

Jung-hwan Park

Tae-jin Park

Do-Jun Byun

Hichan Moon

Min-Su Choi

Jun-Hyeok Ahn

Woo-song Ahn

Sung-Wook Won

Kyung-Tae Chung

Do-Yeong Lee

Hyo-Jin Park

Dong-Min Han

Woo-Song Ahn

A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

Semiconductor devices

An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.

Integrated circuit device and method of manufacturing the same

An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

Method of forming an integrated circuit device including a lower electrode on a sidewall of a support column extending vertical on a top surface of a substrate, a dielectric layer surrounding the support column and the lower electrode, and an upper electrode surrounding the dielectric layer

An integrated circuit device includes a gate stack structure on a base layer, the gate stack structure having a gate insulating layer with a first dielectric layer on the base layer and having first relative permittivity, and a gate structure on the gate insulating layer, and a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including a buried dielectric layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure on the base layer, and the buried dielectric layer including a same material as the first dielectric layer.

Integrated circuit device including gate spacer structure

The present disclosure relates to technology for a sensor network, machine to machine (M2M) communication, machine type communication (MTC), and the Internet of Things (IoT). The present disclosure can be utilized in intelligent services (such as smart home, smart building, smart city, smart car or connected car, healthcare, digital education, retail business, security and safety-related services) based on the technology. The present disclosure relates to a method for a terminal for a position-based service, comprising the steps of: detecting a first signal related to a position of the position-based service in a first mode of scanning the first signal; and determining whether to switch to a second mode of transmitting a second signal related to a position of the terminal according to second mode related information included in the first signal.

Method and device for position-based service

An integrated circuit device includes: a substrate having a cell array area, which includes a first active region, and a peripheral circuit area, which includes a second active region; a direct contact connected to the first active region in the cell array area; a bit line structure connected to the direct contact in the cell array area; and a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure includes two doped semiconductor layers each being doped with a charge carrier impurity having different doping concentrations from each other.

Integrated circuit device

The present disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for internet of things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method for detecting a counterfeit advertiser by a server includes detecting a random delay time or a cumulative interval for a reference device based on a time stamp for an advertisement packet received from the reference device, and detecting a random delay time or a cumulative interval for a receiving device other than the reference device based on a time stamp for an advertisement packet received from the receiving device.

Apparatus and method for detecting counterfeit advertiser in wireless communication system

Integrated circuit device including a support pattern, a lower electrode pattern, a dielectric structure, and an upper electrode structure

An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

Integrated circuit devices

A semiconductor device includes first wiring line patterns on a support layer, second wiring line patterns on the first wiring line patterns, and a multiple insulation pattern. The first wiring line patterns extend in a first direction and are spaced apart from each other in a second direction. The support layer includes first contact hole patterns between the first wiring line patterns that are spaced apart from each other in the first and second directions. The second wiring line patterns extend in the second direction perpendicular and are spaced apart from each other in the first direction. The multiple insulation pattern is on an upper surface of the support layer where the first contact hole patterns are not formed, arranged in a third direction perpendicular to the first direction and the second direction, and between the first wiring line patterns and the second wiring line patterns.

Semiconductor device including contact structure

A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.

Semiconductor device including a bit line

A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern.

Semiconductor device

Growing community of inventors

Hwaseong-si, South Korea

Ki-Seok Lee