Samsung Electronics Co., Ltd.

Ki-sang Kang

Se-Jang Oh

Jeong-Ho Bang

Sung-mo Kang

Seok-ho Park

A semiconductor integrated circuit wafer tester includes a supporting plate on which a semiconductor wafer may be positioned and a tester head having a circular top plate installed a predetermined distance away from the supporting plate, wherein a probe card in the tester head that includes a circular printed circuit board having a diameter of at least 400 mm (15.75 inches) that is connected to the top plate and having a plurality of probe units formed on the printed circuit board allows electrical parameters of multiple chips formed on the semiconductor wafer to be measured simultaneously.

Probe card for tester head

A test method of a tester of a semiconductor memory device which includes recording a test pattern into the semiconductor memory device, reading the recorded test pattern to compare with a expected pattern, detecting information on a defect of the semiconductor memory device with a result of the comparison and interpreting the information on the defect of the semiconductor memory device, the method comprising the steps of: setting up minimum and maximum values relevant to a desired capacity of the semiconductor memory device to be tested; counting up from the preset minimum to the preset maximum values; generating a carry signal by comparing the preset maximum value with the counted value when the counted value gets to the preset maximum value; and resetting a value to be counted if the carry signal is generated, to thereby generate addresses of the semiconductor memory device, and a tester of the semiconductor memory device comprising: minimum and maximum address registering means for saving minimum and maximum address values relevant to a desired capacity of the semiconductor memory device to be tested; address counting means for increasingly counting from the minimum value to generate addresses; and carry signal generating means for generating carry signals, if the addresses output from the address counting means and a signal output from the maximum address registering means are the same, to thereby reset the address counting means, so that a user of the tester does not have to make a new test program, providing convenience in performing a test and improving reliability in results of the test.

Tester of semiconductor memory device and test method thereof

The present invention relates to a semiconductor device testing system having an advanced testing capability for performing tests on a semiconductor device. A system frame includes both normal and high-speed testing formatters, and a test head is arranged in electrical communication with the system frame. Normal PIN drivers are included to operate the testing system at a first frequency to transmit the signals required to perform tests at a normal speed. High-speed PIN drivers are also included to operate the testing system at a second frequency, higher than the first frequency, to transmit the signals required to perform tests at a higher speed. In this manner, the testing system of this invention is able-to achieve superior testing performance while reducing the overall system production cost.

Semiconductor device testing system

A wafer probing system, and a wafer-probing needle calibrating method using the same are provided. The system comprises a main support, a wafer chuck mounted on the main support, a needle chuck for contacting one of the plurality of needles. The needle chuck is comprised of a conductive signal line, and a shield line for shielding the signal line. Further, the system includes positioning means, for determining the position of the plurality of needles, moving means, for vertically moving the needle chuck, being coupled to the support, and means for horizontally moving the support based on the determined position of the plurality of needles. With the present invention system and method, signals applied to wafer probing needles can be accurately calibrated.

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Suwon, South Korea

Ki-sang Kang