Daewoo Electronics Co., Ltd.

Ki Paek Kwon

A method compensates a phase delay of a clock signal used in a data communications system. First, a plurality of delayed clock signals are provided by modifying the amount of delay of the clock signal. In synchronization with one of the delayed clock signals, one or more test data signals and their address signals are sequentially issued and sent to a storage device. In synchronization with the original clock signal, each test data signal is stored in an area that its address signal indicates and then, upon receipt of the address signal at a predetermined time of the original clock signal, a data signal which corresponds to the address signal is read and sent to a controller. At a predetermined time of the delayed clock signal, a data signal is received from the storage device and it is checked whether or not each test data signal and the received data signal are the same. If it is checked to be positive, the process is repeated for a next test data signal and, if otherwise, the process is repeated for a next delayed clock signal until it becomes checked to be positive. Finally, if it is checked to be positive with respect to all the one or more test data signals, the delayed clock signal is decided as a definitive clock signal to be used in the semiconductor device, and if not, the process is repeated for a next delayed clock signal until it becomes checked to be positive.

Method for compensating a phase delay of a clock signal

A reversible adiabatic logic circuit includes a forward logic function circuit, a reverse logic function circuit, a compensation circuit and a clamping circuit. The forward logic function circuit driven by a first clock among power supply clocks having 8 phases during one time period, computes a forward logic function of a complimentary dual rail circuitry using NMOS transistors and determines charging paths of output nodes. The reverse logic function circuit driven by a second clock behind the first clock by two phases, computes a reverse logic function of the complimentary dual rail circuitry using NMOS transistors and determines discharging paths of output nodes. The compensation circuit compensates a decrease in the swing in the output nodes due to thresholds of the NMOS transistors. The computing units of the forward logic function and the reverse logic function are implemented by NMOS transistors only, and the decrease in the swing of the NMOS transistors is compensated using a pair of PMOS transistors. Therefore, non-adiabatic energy dissipation can be avoided, and the area occupied by the circuit can be greatly reduced compared to the conventional computing units implemented by transmission gates.

Growing community of inventors

Seoul, South Korea

Ki Paek Kwon