Samsung Electronics Co., Ltd.

Ki-nam Kim

Hong-sik Jeong

Won-Suk Yang

Won-suk Yang

Byung-Gil Jeon

Yoon-jong Song

Hong-Sik Jeong

Yoo-Sang Hwang

Chang-hyun Cho

Sang-Woo Lee

Ji-young Kim

Joo-young Lee

Sang-hyeon Lee

Dong-won Shin

Sang-Ho Song

Yoon-soo Chun

Sang-Hoo Song

Heung-jin Joo

Min-hee Cho

Su-Jin Ahn

Se-myeong Jang

Dong-jin Jung

Soo-ho Shin

Yoo-sang Hwang

Young-nam Hwang

Gwan-byeob Koh

Byung-hyug Roh

A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a width of an entrance portion adjacent to the surface of the ILD layer larger than the width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a width larger than that of the second contact stud. The second contact stud has a width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad. The entrance portion of the first contact stud has a width about 30-60% larger than that of the contacting portion.

Semiconductor device having multilayer interconnection structure and manufacturing method thereof

A semiconductor device and a method for fabricating the same are provided. The provided semiconductor device includes a field oxide layer formed in a semiconductor substrate to define an active region; gate structures formed on the active region; source/drain junctions formed on either side of the gate structures on the semiconductor substrate; a channel silicon layer arranged under the gate insulating layer to operate as a channel for connecting sources and drains; and buried junction isolation insulating layers under the channel silicon layer. The buried junction isolation insulating layers isolate source/drain junction regions of a MOS transistor, so that a short circuit in a bulk region under the channel of a transistor due to the high-integration of the device can be prevented.

Method of fabricating semiconductor device having junction isolation insulating layer

A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a pad. At least one plug is formed in a first interlayer insulating layer and the lower part of a second interlayer insulating layer. The second interlayer insulating layer is divided into a plurality of interlayer insulating layers so that upper and lower widths of the divided plugs formed in the divided portion of the second interlayer insulating layer are not greatly different from each other. The pad formed on the upper portion of the second interlayer insulating layer has an upper width such that the upper conductive layer connected to the pad is not undesirably connected to an adjacent upper conductive layer via the pad.

Semiconductor memory device and method for manufacturing the same

Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.

Ferroelectric integrated circuit devices having an oxygen penetration path

Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

Ferroelectric memory devices having a plate line control circuit

An integrated circuit device is manufactured by forming an insulating layer on a substrate. A capping layer is formed on the insulating layer and both the capping layer and the insulating layer are patterned. Insulating spacers are formed on sidewalls of the insulating layer so that the insulating spacers, the capping layer, and the substrate enclose the insulating layer.

Methods of manufacturing integrated circuit devices having an encapsulated insulation layer

An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions. A plurality of bit line structures are on the substrate, extending transverse to the word line structures and contacting the second conductive pads. Related methods of fabrication are also described.

Methods of fabricating integrated circuit devices including self-aligned contacts with increased alignment margin

An integrated circuit device structure which avoids misalignment when a contact hole is formed to expose a contact pad and a method of fabricating the same, are provided. The integrated circuit device includes a semiconductor substrate having a conductive region and an insulating region, a contact pad on the conductive region of the semiconductor substrate, an auxiliary pad adjacent to the contact pad, and an interlevel insulating layer on the semiconductor substrate and having a contact hole for exposing both the contact pad and the auxiliary pad.

Integrated circuit devices with an auxiliary pad for contact hole alignment

Ferroelectric memory devices having a plate line control circuit and methods for operating the same

Semiconductor device and method for fabricating the same

A phase-change memory device includes a phase-change memory cell having a volume of material which is programmable between amorphous and crystalline states. A write current source selectively applies a first write current pulse to program the phase-change memory cell into the amorphous state and a second write current pulse to program the phase-change memory cell into the crystalline state. The phase-change memory device further includes a restore circuit which selectively applies the first current pulse to the phase-change memory cell to restore at least an amorphous state of the phase-change memory cell.

Phase-change memory and method having restore function

Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the Ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.

Methods of forming an integrated circuit device may include forming first and second spaced apart source/drain regions on a surface of a semiconductor substrate. A gate insulating layer can be formed on the semiconductor substrate extending between the first and second spaced apart souce/drain regions. The gate insulating layer can have a reduced thickness at a central portion thereof between the first and second spaced apart source/drain regions. A thickness of the gate insulating layer can increase as it extends toward each of the source/drain regions. A gate electrode can be formed on the gate insulating layer such that the gate insulating layer is between the semiconductor substrate and the gate electrode. Related devices are also discussed.

Methods providing oxide layers having reduced thicknesses at central portions thereof

Integrated circuit devices including self-aligned contacts with increased alignment margin

According to embodiments of the present invention, methods of manufacturing a semiconductor device, and semiconductor devices manufactured thereby, are provided. A field region is formed that defines active regions in a semiconductor substrate. Spaced apart gates are formed on the active regions in the semiconductor substrate. The gates have sidewalls that extend away from the semiconductor substrate. First spacers are formed on the sidewalls of the gates. Second spacers are formed on the first spacers and opposite to the gates. Ion impurities are implanted into the active regions in the semiconductor substrate, adjacent to the gates, using the first and second spacers as an ion implantation mask. A portion of the second spacers is removed to widen the gaps between the gates. A dielectric layer is formed on the semiconductor substrate in the gaps between the gates.

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Kyungki-do, South Korea

Ki-nam Kim