Skhynix Inc.

Ki Myung Kyung

Hyung Soo Kim

Ki Won Lee

Ic Su Oh

Jung Hyuk Yoon

Mun Phil Park

Kyu Nam Lim

Myoung Jin Lee

Hong Sok Choi

Sun Hwa Park

A variable resistive memory device includes a memory cell array and a control circuit block. The memory cell array includes a plurality of memory cells that are connected between a global word line and a global bit line. The control circuit block is positioned on at least one of edge portions of the memory cell array. The memory cell array is classified into a first group with the memory cells that are adjacent to the control circuit block and a second group with the memory cells that are remote in relation to the control circuit block. The second group is farther from the control circuit block than the first group. The control circuit block includes a write control unit that generates a control signal for writing on the memory cell in the first group in a different way compared to writing on the memory cell in the second group.

Variable resistive memory device and method of operating the same

A semiconductor memory apparatus may be provided. The semiconductor memory apparatus may include a memory element. The semiconductor memory apparatus may include a first switching driving circuit coupled to the memory element. The semiconductor memory apparatus may include a second switching driving circuit coupled to the memory element.

Semiconductor memory apparatus

A variable resistive memory device may include a memory region and controller. The memory region may include a plurality of unit memory cells each electrically connected between a word line and a bit line. The controller may perform a driving operation of the word line in response to a read command. The controller may perform a driving operation of a bit line to output cell data through the bit line substantially simultaneously with the driving operation of the word line. Each of the unit memory cell may include a variable resistive material.

Variable resistive memory device including controller for driving bitline, word line, and method of operating the same

A resistive memory apparatus includes a plurality of bit lines, a plurality of local bit lines, and a plurality of global bit lines. The plurality of bit lines is electrically coupled to a plurality of memory cells. The plurality of local bit lines are extended in a row direction, and electrically coupled to one or more of the plurality of bit lines. The plurality of global bit lines are extended in the column direction, and electrically coupled to one or more of the plurality of local bit lines.

Resistive memory apparatus having hierarchical bit line structure

A bit line sense amplifier control circuit is configured to drive a bit line sense amplifier according to a first sense amplifier enable signal and a second sense amplifier enable signal, wherein the driving force of the bit line sense amplifier is changed in response to a column selection control signal.

Bit line sense amplifier control circuit and semiconductor memory apparatus having the same

A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation.

Sense amplifier and semiconductor apparatus including the same

Various embodiments of a semiconductor memory apparatus and a related driving method are disclosed. According to one exemplary embodiment, a semiconductor memory apparatus may include a switching unit and a switching control unit. The switching unit couples or decouples a cell plate voltage line to or from a cell plate electrode in response to a control signal. The switching control unit is configured to enable the control signal at a first timing and disable the control signal at a second timing.

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Icheon-si, South Korea

Ki Myung Kyung