Samsung Electronics Co., Ltd.

Ki-Kwon Jeong

Hyeon Deuk Hwang

Dong-Kuk Kim

In-Young Lee

Kwang-Yong Lee

Hyun-Jun Kim

Cheol-Joon Yoo

Jong-Gi Lee

Hyeong-Seob Kim

Chang-Cheol Lee

Min-Ill Kim

Young-shin Choi

Seung-Bae Jeong

A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.

Semiconductor package including semiconductor chip with through opening

An in-line package apparatus includes a first treating unit, an input storage unit, a heating unit and an output storage unit. The first treating unit performs a ball attach process or a chip mount process. A processing object that a process is completed in the first treating unit is received in a magazine so as to be vertically stacked and a plurality of magazines each having one or more processing objects is stored in an input stacker. The heating unit performs a reflow process on the processing objects in the magazine stored in the input stacker by an induction heating method. A processing object that a reflow process is completed is received in a magazine and then stored in an output stacker.

In-line package apparatuses and methods

A method of aligning a wafer includes recognizing images of the wafer accommodated on a work table and a notch of the wafer using a camera, designating at least one notch point of the notch in a recognized image, producing at least one reference line using the designated notch point in the recognized image, designating a center point of the reference line in the recognized image, producing an imaginary line having an angle with respect to the reference line from the center point of the reference line in the recognized image, producing a center line of the wafer using the imaginary line in the recognized image, and aligning the wafer using an alignment apparatus to allow the center line of the wafer and an alignment line of the work table to be matched.

Method for aligning wafer and alignment apparatus using the method

A method of forming a stack of thin wafers provides a wafer level stack to greatly reduce process time compared to a method where individually separated chips are stacked after a wafer is sawed. A rigid planar wafer support member stabilizes and planarizes each wafer while it is thin or its thickness is reduced and during subsequent wafer processing. Thinned wafers are stacked and the external support members are removed by applying heat or ultraviolet (UV) light to an expandable adhesive layer between the support members and the thin wafers. The stacked wafers then can be further processed and packaged without thin-wafer warping, cracking or breaking. A wafer level package made in accordance with the invented method also is disclosed.

Method of forming a thin wafer stack for a wafer level package

A method may involve mounting a first supporting plate on an active surface of a wafer using an adhesive. A portion of the back surface of the wafer may be backlapped. A second supporting plate may be mounted on the back surface of the wafer using an adhesive. The first supporting plate may be removed from the active surface of the wafer. Conductive bumps may be provided on the active surface. A backlapping process may include a first grinding process, a second grinding process, and a polishing process. The first and the second supporting plates may be fabricated from a solid material. The adhesive may be an ultraviolet cure adhesive or a thermal cure adhesive.

Method for manufacturing semiconductor wafer

Provided is a method by which differently-sized chips may be stacked at the wafer level. The wafer level chip stack method utilizes first and second wafer assemblies that support first and second wafers on adhesive tapes. One or both of the supported wafers may be sawed or otherwise divided to obtain separate first and second chips that remain fixed to respective first ring frames. The first and second wafer assemblies may then be positioned and aligned so that a back surface of the second wafer faces an active surface of the first wafer. Each of the second chips may then be bonded to a corresponding first chip to form a chip stack using an adhesive layer. The chip stacks may then be detached from the wafer assemblies and attached to a substrate.

Wafer level chip stack method

A die attaching method of a semiconductor chip simplifies the process of fabricating a package from the chip while preventing the chip form being damaged even when the chip is very thin. Warpage prevention material is adhered to a top surface of a wafer having a plurality of chips formed thereon, and then the wafer is cut to separate the chips from one another. Each semiconductor chip is then placed on and attached to a die pad of a base frame, while the warpage prevention material is detached from the semiconductor chip. Thus, the warpage prevention material is removed without requiring a process that is extraneous to the die attaching process.

Die attaching method of semiconductor chip using warpage prevention material

A method of utilizing a removable protective tape to protect the active surfaces of semiconductor wafer and the individual semiconductor chips during semiconductor packaging processes is provided along with several configurations of apparatuses that may be used in such a method for removing protective tape portions from individual semiconductor chips during the assembly process.

Protective tape removing apparatus and method of assembling semiconductor package using the same

A dicing tape attaching unit that can attach both a pre-cut dicing tape and a general dicing tape to a wafer in a semiconductor package assembling process, and an in-line system used in a semiconductor package process including the dicing tape attaching unit are provided. The dicing tape attaching unit supplies one of the pre-cut dicing tape and the general dicing tape and attaches it to a wafer according to the direction of rotation of a tape loader. Accordingly, without an additional pre-cut dicing tape attaching unit, either of the pre-cut dicing tape and the general dicing tape can be attached to the back side of the wafer by one and the same unit.

In line system used in a semiconductor package assembling

An automatic wafer backside inspection may automatically inspect a backside of a semiconductor wafer to look for contamination, cracks, scratches and the like. An inspection apparatus may comprise a wafer cassette with slots to hold a plurality of wafers. A wafer transfer arm may be located near the wafer cassette. A wafer flip/aligner may be operable to flip and align wafers. A wafer inspecting unit may be located adjacent the wafer flip/aligner and be operable to inspect the backside of wafers flipped by the flipper aligner. A wafer buffer stage may be located between the wafer cassette and the wafer flip/aligner for temporarily holding a wafer. The wafer transfer arm may transfer wafers to/from or amongst at least two of the wafer cassette, the wafer flip/aligner, the wafer inspection unit and the wafer buffer stage.

Apparatus and method for wafer backside inspection

A semiconductor chip is provided comprising a semiconductor substrate having determined circuit elements on it, a surface-smoothing layer deposited on the substrate, a bonding pad formed on the smoothing layer and connected electrically to the circuit elements, a passivation layer formed on the surface-smoothing layer, the passivation layer having a window for exposing a part of the bonding pad, and a second metal layer having a same height as the passivation layer and occupying peripheral parts of the window to form a reduced bonding windows for the bonding pad.

Growing community of inventors

Cheonan-si, South Korea

Ki-Kwon Jeong