Samsung Electronics Co., Ltd.

Ki-Kwan Park

Kyoung-woo Lee

Jae-hak Kim

Hong-Jae Shin

Seung-Jin Lee

Young-jin Wee

Soo-geun Lee

Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.

Method for forming interconnection line in semiconductor device and interconnection line structure

The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.

Method of forming interconnection lines for semiconductor device

In order to avoid a faulty pattern resulting from a photoresist tail being formed due to a step difference of an upper hard mask layer when a dual hard mask layer is used, a planarization layer is formed following patterning of the upper hard mask layer. In this manner, a photoresist pattern is formed without the creation of a photoresist tail. Alternatively, a single hard mask layer and a planarization layer are substituted for the dual lower hard mask layer and an upper hard mask layer, respectively. In this manner, it is therefore possible to form a photoresist pattern without a photoresist tail being formed during photolithographic processes. In order to prevent formation of a facet, the planarization layer is thickly formed or, alternatively, the hard mask layer is etched using the photoresist pattern.

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Busan-si, South Korea

Ki-Kwan Park