Skhynix Inc.

Ki Jun Sung

Jong Hoon Kim

Young Geun Yoo

Hyeong Seok Choi

Ki Bum Kim

Sang Yong Lee

Jong Hyun Nam

Han Jun Bae

Seung Jee Kim

Chae Sung Lee

Yeon Seung Jung

Pil Soon Bae

Ha Gyeong Song

Kyoung Tae Eun

Sungkyu Kim

Rae Hyung Jeong

Sang Hyuk Lim

A stack package, and a method of manufacturing the same, includes a first encapsulant layer formed on a carrier. Also semiconductor dies are sequentially offset stacked on the first encapsulant layer. Vertical connectors connected to the semiconductor dies are formed. A second encapsulant layer coupled to the first encapsulant layer is formed to encapsulate the vertical connectors and the semiconductor dies. Redistribution layers connected to the vertical connectors are formed on the second encapsulant layer.

Stack packages and methods of manufacturing the same

A semiconductor package includes an outer redistributed line (RDL) structure, a first semiconductor chip disposed on the outer RDL structure, a stack module stacked on the first semiconductor chip, and a bridge die stacked on the outer RDL structure. A portion of the stack module laterally protrudes from a side surface of the first semiconductor chip. The bridge die supports the protruding portion of the stack module. The stack module includes an inner RDL structure, a second semiconductor chip disposed on the inner RDL structure, a capacitor die disposed on the inner RDL structure, and an inner encapsulant. The capacitor die acts as a decoupling capacitor of the second semiconductor chip.

Semiconductor package including a bridge die

A semiconductor package may include: at least one semiconductor chip disposed such that an active surface on which a plurality of chip pads are disposed faces a redistribution conductive layer; a plurality of vertical interconnectors, each with one end connected to a respective chip pad, extending in a vertical direction toward the redistribution conductive layer; a molding layer covering the semiconductor chip and the vertical interconnectors while exposing an other end of each of the vertical interconnectors that is not connected to the chip pad; a plurality of landing pads disposed over the molding layer, and each connected to the other end of each of the vertical interconnectors; a redistribution insulating layer covering the molding layer with an opening that collectively exposes the landing pads; and the redistribution conductive layer that extends over the molding layer and the redistribution insulating layer while being connected to each of the landing pads.

Semiconductor package including vertical interconnector

A system-in-package includes a redistributed line (RDL) structure, a first semiconductor chip, a second semiconductor chip, and a bridge die. The RDL structure includes a first RDL pattern to which a first chip pad of the first semiconductor chip is electrically connected. The second semiconductor chip is stacked on the first semiconductor chip such that the second semiconductor chip protrudes past a side surface of the first semiconductor chip, wherein a second chip pad disposed on the protrusion is electrically connected to the first RDL pattern through the bridge die.

System-in-packages including a bridge die

A stack package includes a plurality of sub-packages vertically stacked. Each of the sub-packages includes a bridge die having a plurality of vertical interconnectors and a semiconductor die. A first group of vertical interconnectors disposed in a first bridge die included in a first sub-package of the sub-packages and other vertical interconnectors connected to the first group of vertical interconnectors constitute a first electric path, and a second group of vertical interconnectors disposed in a second bridge die included in a second sub-package of the sub-packages and other vertical interconnectors connected to the second group of vertical interconnectors constitute a second electric path. The first and second electric paths are electrically isolated from each other and disposed to provide two separate electric paths.

Stack packages including bridge dies

A semiconductor package includes first and second semiconductor dies, first and second redistributed line structures, a first bridge die, and a vertical connector. The first semiconductor die and the first bridge die are disposed on the first redistributed line structure. The first bridge die is disposed to provide a level difference between the first semiconductor die and the first bridge die, the first bridge die having a height that is less than a height of the first semiconductor die. The second redistributed line structure has a protrusion, laterally protruding from a side surface of the first semiconductor die when viewed from a plan view, and a bottom surface of the second redistributed line structure is in contact with a top surface of the first semiconductor die. The second semiconductor die is disposed on the second redistributed line structure. The vertical connector is disposed between the bridge die and the protrusion of the second redistributed line structure to support the protrusion.

Semiconductor packages including bridge die

A semiconductor package includes a semiconductor die and a bridge die. The bridge die includes through vias, and the through vias are connected to post bumps. The through vias are electrically connected to the semiconductor die by redistribution lines.

Semiconductor packages including bridge die spaced apart from semiconductor die

A stack package includes a first sub-package, a second sub-package stacked on the first sub-package. The first sub-package is configured to include first and second semiconductor dies, a first flexible bridge die disposed between the first and second semiconductor dies.

Stack packages relating to bridge die

A stack package includes a second sub-package stacked on a first sub-package. The stack package also includes a plurality of dummy balls located between the first and second sub-packages to support the second sub-package. Each of the first and second sub-packages includes a semiconductor die and a bridge, die which are spaced apart from each other.

Semiconductor packages are provided. The semiconductor package includes a first semiconductor chip to which a first elevated pillar bump is connected, a second semiconductor chip stacked on the first semiconductor chip to leave revealed the first elevated pillar bump and configured to include a first chip pad disposed on a center region of the second semiconductor chip, a third semiconductor chip offset and stacked on the second semiconductor chip to leave revealed the first chip pad, and a chip supporter supporting an overhang of the third semiconductor chip.

Semiconductor packages including a multi-chip stack

A chip stack package includes first and second semiconductor chips. A first redistribution line structure is disposed on a front surface of the first semiconductor chip, and the first redistribution line structure extends onto a side surface of the first semiconductor chip. A second redistribution line structure is disposed on the front surface of the first semiconductor chip, and the second redistribution line structure extends onto the side surface of the first semiconductor chip. A third redistribution line structure is disposed on a front surface of the second semiconductor chip, and the third redistribution line structure extends onto a side surface of the second semiconductor chip to be electrically connected to the second redistribution line structure.

Chip stack packages

A semiconductor package may be provided. The semiconductor package may include a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer. The semiconductor package may include a heat transferring block disposed between the first and second semiconductor chips to be mounted on the interconnection layer. Related methods are also provided.

Semiconductor packages including heat transferring blocks and methods of manufacturing the same

A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.

Manufacturing methods semiconductor packages including through mold connectors

There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.

Semiconductor packages including heat spreaders and methods of manufacturing the same

There is provided a structure and a method of manufacturing a semiconductor package. The method includes disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, and mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

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Cheongju-si, South Korea

Ki Jun Sung