Samsung Electronics Co., Ltd.

Industry-University Cooperation Foundation Hanyang University

Pohang University of Science and Technology Foundation

Soongsil University

Ki-Jun Lee

Myung-Kyu Lee

Jun Jin Kong

Jun-Jin Kong

Hong-Rak Son

Sung-Hye Cho

Dae-Hyun Kim

Yong-Gyu Chu

Young-Jun Hwang

Jaehong Kim

Jae-Hong Kim

Kyeong-Cheol Yang

Dong-Min Shin

Jin-Ki Kim

Pil-sang Yoon

Yong-June Kim

Dong-Joon Shin

Chang-Kyu Seol

Seong-Hyeog Choi

Hyung-June Kim

Sung-Rae Kim

Seung-Chan Lim

Se-Jin Lim

Hee-seok Eun

Geun-Yeong Yu

Sung-Han Jung

An error correction code (ECC) circuit of a semiconductor memory device includes a syndrome generation circuit and a correction circuit. The syndrome generation circuit generates syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal. The correction circuit receives the codeword, corrects at least a portion of (t1+t2) error bits in the codeword based on the syndrome and outputs a corrected message. Here, t1 and t2 are natural numbers, respectively.

Error correction code circuits, semiconductor memory devices and memory systems

A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

Semiconductor memory devices and memory systems including the same

An error correcting circuit receives a codeword including user data and a parity code, and performs an error correction operation on the user data. The circuit includes a first buffer, a decoder, a second buffer and a processor. The first buffer stores the codeword and sequentially outputs pieces of subgroup data obtained by dividing the codeword. The decoder generates pieces of integrity data for each of the pieces of subgroup data received from the first buffer, and performs the error correction operation on the user data using the parity code. The second buffer sequentially stores the pieces of integrity data for each of the pieces of subgroup data. The processor determines whether an error is present in the codeword based on the pieces of integrity data stored in the second buffer when at least one of the pieces of integrity data is updated in the second buffer.

Error correcting circuit performing error correction on user data and error correcting method using the error correcting circuit

An error correction code (ECC) decoder of a semiconductor memory device is provided. The ECC decoder includes an ECC checker, a syndrome generator, and an error detection/correction circuit. The ECC checker generates characteristic information representing first error information associated with message bits in an input codeword that is read from a target page in a memory cell array. The syndrome generator outputs a syndrome vector representing second error information associated with the input codeword by performing an operation on the message bits and parity bits in the input codeword based on a parity check matrix. The an error detection/correction circuit generates a transmission codeword by selectively correcting an error bit in the input codeword based on the characteristic information and the syndrome vector, generates a flag signal indicating whether the transmission codeword includes an error bit, and outputs a transmission message based on the transmission codeword.

Error correction code decoders, semiconductor memory devices and memory systems

A method of decoding a low density parity check (LDPC) code, includes dividing a parity check matrix of the LDPC code, into a plurality of sub blocks. The method further includes, for each of a plurality of decoding iterations, performing a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule, estimating a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks, and adjusting the decoding schedule, based on the reliability of each of the target sub blocks.

Method of decoding low density parity check (LDPC) code, decoder and system performing the same

A method of operating a memory system, having a non-volatile memory device, includes processing a response to a first request toward the memory device by using an original key, in response to the first request, generating and storing first parity data corresponding to the original key, and deleting the original key.

Memory device, memory system, and method of operating the memory system

A list decoding method for a polar code includes generating a tree-type decoding graph for input codeword symbols; the generating a tree-type decoding graph including, generating a decoding path list to which a decoding edge is added based on a reliability of a decoding path, the decoding path list being generated such that, among decoding paths generated based on the decoding edge, decoding paths within a threshold number of critical paths survive within the decoding path list in an order of high likelihood probability, and determining an estimation value, which corresponds to a decoding path having a maximum likelihood probability from among decoding paths of the decoding path list, as an information word.

List decoding method for polar code and memory system using the same

An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data.

Interleaving apparatuses and memory controllers having the same

An encoding device includes an encoder and a puncturing unit. The encoder generates parity bits based on information bits. The puncturing unit punctures the parity bits based on a puncturing pattern complying with a first criterion determining a period of the puncturing pattern and a second criterion determining positions of remaining parity bits.

Encoding device, controller and system including the same

An apparatus and method for controlling an operating mode in a semiconductor memory device is provided. During test mode, test mode selection signals are supplied to the memory device according to test mode commands received from an external pad and decoded internally. During both test mode and user mode, user mode selection signals are supplied to the memory device according to user mode commands received from an external pad and decoded internally. Upon receipt of a test release command, test mode commands are fusably disabled, such that entry into test mode and decoding of test mode commands is thereafter prevented.

Apparatus and method for controlling operating mode in semiconductor

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Seoul, South Korea

Ki-Jun Lee