Samsung Electronics Co., Ltd.

Phicom Corporation

Ki-Joon Kim

Kil-Ho Lee

Cheol-Kyu Kim

Tae-Yon Lee

Se-Woong Park

Yong-Hwi Jo

Yoon-Ho Khang

Sung-Bong Kim

Bum-seok Seo

Youn-seon Kang

Jun-Ho Lee

Jong-Mil Youn

Dong-seok Suh

Yong-Jun Kim

Jong-Seon Kim

Hyung-joon Kwon

Yong-Yun Park

Myoung-Su Son

Matthias Wuttig

Daniel Wamwangi

Jong-mil Youn

Min-Hwa Jang

Sung-Young Oh

Jun-Tae Hwang

A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in the layer, and a mask layer is formed in the first trench. The mask layer has a first thickness from a bottom surface of the first trench to the top of the mask layer. The mask layer is patterned to form a mask that at least partially exposes a sidewall of the first trench. A portion of the mask adjacent to the exposed sidewall of the first trench has a second thickness smaller than the first thickness. The layer is etched to form a second trench using the mask as an etching mask. The second trench is in fluid communication with the first trench. A conductive pattern is formed in the first trench and the second trench.

Semiconductor structures having an insulative island structure

Semiconductor structures and methods of manufacturing the same

An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.

Methods of forming patterns and methods of manufacturing semiconductor devices using the same

Nonvolatile memory devices and methods of fabricating the same, include, forming a transistor in a first region of a substrate, forming a contact which is connected to the transistor, forming an information storage portion, which is disposed two-dimensionally, in a second region of the substrate, sequentially forming a stop film and an interlayer insulating film which cover the contact and the information storage portion, forming a first trench, which exposes the stop film, on the contact, and forming a second trench which extends through the stop film to expose the contact, wherein a bottom surface of the first trench is lower than a bottom surface of the information storage portion.

Nonvolatile memory devices and methods of fabricating the same

A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern.

Method of manufacturing a semiconductor device

A timing controller that includes a noise detection circuit and a setting control unit. The noise detection circuit includes a detection unit and a reset signal generating unit. The detection unit outputs a detection signal having a first logic level based on at least one of a plurality of reference data toggling asynchronous with a clock signal. The reset signal generating unit outputs a reset signal having a second logic level based on the detection signal. The setting control unit stores setting data and initializes the setting data in response to the reset signal having the first logic level, and the setting data are used to process red, green and blue (RGB) image data.

Timing controller and a display device including the same

A magnetic body structure including: a magnetic layer pattern; and a conductive pattern including a metallic glass alloy and covering at least a portion of the magnetic body structure.

Magnetic device having a metallic glass alloy

There is provided a source driver capable of controlling the timing of source line driving signals in a liquid crystal display device. The source driver includes a plurality of output circuits, each output circuit including an output buffer and a switch. The output buffer amplifies an analog image signal, and the switch outputs the amplified analog image signal as a source line driving signal in response to a control signal. The source driver further comprises a control circuit for generating the control signal, the control circuit comprising: a delay circuit delaying a switch signal and generating a delayed switch signal; and a multiplexer selecting one of the switch signal and the delayed switch signal in response to a selection signal and outputting the selected signal as the control signal.

Source driver capable of controlling source line driving signals in a liquid crystal display device

In a method of manufacturing a probe card, a plurality of probe modules, including a sacrificial substrate and probes on the sacrificial substrate, is prepared. The probe modules are mutually aligned to form a probe module assembly having the aligned probe modules and a desired size. The probe module assembly is then attached to a probe substrate. Thus, the probe card having a large size may be manufactured.

Method and apparatus for manufacturing a probe card

A method of operating a phase-change memory device, including a phase-change layer and a unit applying a voltage to the phase-change layer, which includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.

Method of operating a phase-change memory device

A phase change material layer includes antimony (Sb) and at least one of indium (In) and gallium (Ga). A phase change memory device includes a storage node including a phase change material layer and a switching device connected to the storage node. The phase change material layer includes Sb and at least one of In and Ga.

Phase change material layers and phase change memory devices including the same

Disclosed may be a phase change material alloy, a phase change memory device including the same, and methods of manufacturing and operating the phase change memory device. The phase change material alloy may include Si and Sb. The alloy may be a Si&#x2014;O&#x2014;Sb alloy further including O. The Si&#x2014;O&#x2014;Sb alloy may be SiOSb, wherein, when x/(x+z) may be x, 0.05&#x2266;x&#x2266;0.30, 0.00&#x2266;y&#x2266;0.50, and x+y+z may be 1. The Si&#x2014;O&#x2014;Sb alloy may further comprise an element other than Si, O, and Sb.

Phase change material, phase change memory device including the same, and methods of manufacturing and operating the phase change memory device

In a method of manufacturing bonding probes, bump layer patterns are formed on terminals of a multi-layered substrate. A first wetting layer pattern having a wettability with respect to a solder paste, and a non-wetting layer pattern having a non-wettability with respect to the solder paste are formed on the bump layer patterns. The solder paste is formed on the first wetting layer and the non-wetting layer pattern. The probes, which make contact with an object, are bonded to the solder paste. The solder paste on the non-wetting layer pattern reflows along a surface of the first wetting layer pattern to form an adhesive layer on the first wetting layer pattern. Thus, a sufficient amount of the solder paste, which is required for bonding the probes, may be provided to firmly bond the probes.

Method of bonding probes and method of manufacturing a probe card using the same

Provided is a phase-change memory using a single-element semimetallic thin film. The device includes a storage node having a phase-change material layer and a switching element connected to the storage node, wherein the storage node includes a single-element semimetallic thin film which is formed between an upper electrode and a lower electrode. Thus, the write speed of the phase-change memory can be increased compared with the case of a Ge&#x2014;Sb&#x2014;Te (GST) based material.

Growing community of inventors

Hwaseong-si, South Korea

Ki-Joon Kim